July 15, 1997
Hitachi to Release the HG73M Series of ASICs that Integrate High Speed Logic and a High Density DRAM on the Same Chip- Adopting a DRAM micromodule architecture for higher performance, lower power consumption, and miniaturization -Recently, there is a strong need for increased performance, miniaturization and reduced power in areas such as portable information processing equipment, image processing devices, storage, and games. For example, in the area of high performance image processing, a high speed of more than 1G byte/ sec. is required for 3D graphics processing. However, it has been difficult to realize such speed in previous systems which use an external DRAM due to the width of the bus between the external DRAM and the logic. Given this background, at the 1996 Symposium on VLSI Circuits, Hitachi announced the development of a test chip , which includes an on-chip 8 Mbit DRAM for 3D graphics, and developed the fundamental technology for combining a DRAM and logic on the same chip. Based on that technology, Hitachi is to release the HG73M series, which can include a high density DRAM. The basic concepts behind Hitachi's ASICs are an extensive cell library, a short design period, and an easy-to-use design environment. Hitachi has already released the HG71 series that adopts a 0.8-micrometer process, the HG72 series that adopts a 0.5-micrometer process, and the HG73 series that adopts a 0.35-micrometer process and includes the HG 73C series which can incorporate either an SH-3(SH7708) or an H8S CPU core. Hitachi has also prepared a development environment based on an ASIC procedure that allows users to design their products themselves. In the logic blocks, this series adopts the 0.35-micrometer CMOS process, which features a 0.35-micrometer gate length and a three-layer metal wiring technology. Random logic is designed using the same cell library as with the HG73C series. A high-level language model is used for the DRAM blocks, and after the user customizes the required number of modules on an engineering workstation, the user simulates the combined DRAM and logic circuit. Hitachi's DRAM modules adopt a DRAM micromodule architecture, which can achieve the high performance and low power consumption required of ASICs that include a DRAM and can flexibly support the diverse memory structures that occur in ASIC products. Hitachi's DRAM micromodule architecture supports scalability and expansion using a 256-Kbit clock-synchronous DRAM micromodule as a single bank unit. For example, a 4-Mbit DRAM module would be constructed from 16 banks. This multi-bank architecture allows independent X-Y address control for each bank, and pipelining memory accesses using a 128 bit wide bus can provide data transfer rates 10 to 100 times those achievable with an external DRAM system. The fabrication process was optimized for combined DRAM/logic systems, and retains the high-speed performance of 0.35-micrometer logic (clock rates up to 150 MHz) and allows the inclusion of large-scale DRAM systems on chip. Since combining DRAM and logic on the same silicon chip allows an internal bus to be used to connect the DRAM to the logic, and allows low-current drive to be used to drive that bus, the bus load can be reduced significantly from that associated with the external bus on the system board used in earlier systems. This allows power requirements to be reduced to 1/10 or 1/20 that required by previous systems. Furthermore, the adoption of the multibank technique allows applications to significantly reduce DRAM module power consumption by only making the selected bank active. This series can incorporate a maximum 140 Mbit DRAM. The maximum amount of DRAM that can be included on a chip is determined by the allocation of chip space between memory and logic for the largest chip size the user can accept from a cost standpoint. For example, a 10-mm square chip can hold 30 Mbits of DRAM if 100% of the chip is used for DRAM, and 16 Mbits of DRAM if 200,000 logic gates are required. In addition to standard QFP packages with between 100 and 296 pins, the HG73M series will also be available in low-thermal expansion QFP packages that include a built- in heat spreader, and in BGA packages with up to 352 pins for high-density high-speed applications. This series will also be available in chip scale packages (CSPs) with between 136 and 262 pins, and 135 to 401-pin PGA ceramic packages, and thus all Hitachi packages that can be used with ASICs can be used with the HG73M series. As is the case with earlier Hitachi's ASICs, the HG73M series supports the use of a consistent design environment based on commercial EDA tools running on an engineering workstation. (These EDA tools include Cadence*, Mentor*, and Synopsys* products.) For DRAM modules, Hitachi also provides a timing information matching model written in a high-level language. Future developments in this HG73M series will include the ability to include Hitachi's high-performance CPU cores and analog modules along with a DRAM and logic. These features are planned for release next spring. Additionally, Hitachi has already established 0.25-micrometer process technology, and is aiming at creating an ASIC system product that can combine CPU cores, analog modules, DRAM, flash memory, and random logic on a single chip.
Application Product Examples
Pricing in Japan
Specifications
Note: Items in angle brackets are under development.
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