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November 4, 1997

Hitachi to Release 2-D Graphics Renderer Chip for the SuperH Family

- For use in consumer information products, featuring on-chip real-time drawing and background display functions -

The recent advent of low-cost computer game systems that offer a high level of both display responsiveness and representational capability in the implementation of their man-machine interface has raised hopes of a dramatic improvement in graphic display capability in the consumer information device market, including car navigation systems and Internet TVs. The conventional approach to meeting these requirements in graphics processing has been to have both geometrical processing(*2) and rendering processing(*3) performed by the CPU, using large-capacity high-speed memory, or to use a graphics chip incorporating as many graphics algorithms as possible. There is a growing need for simpler and more powerful implementation of these kinds of processing, while maintaining upward-compatibility of software and data bases. At the same time, a major concern is how to handle increasingly complex graphics algorithms.

In response to this demand, Hitachi developed the Q Series of graphics accelerators to perform high-speed rendering and display processing in a chip set combined with a SuperH microcomputer. Designed around the concepts of simplicity, real-time capability, and upgradability, a Q Series chip efficiently and inexpensively performs line drawing, surface drawing, and other rendering processing corresponding to coordinate conversion and similar geometrical processing executed by a SuperH microcomputer.

The Q2i incorporates a new background display function that enables animation or similar kinds of action display to be performed in the foreground while scrolling the background. In addition, support for a drawing halt and restart function allows foreground and background drawing to be carried out independently. Drawing functions have also been enhanced and the SuperH interface has been revised, to provide greatly improved ease of use in a SuperH chip set. The Q2i uses the same unified graphics memory architecture(*4) as the Q2(*5) for managing graphics memory. With this architecture, all graphics data, including color graphics for natural images, etc., and data with different data formats, such as fonts and patterns, is managed in the same memory. In addition, cost-efficient EDO (Extended Data Output) DRAM is used for the frame buffers (video display memory). Moreover, four kinds of commands, including a 4-vertex polygon(*6) drawing command that allows free transformation of natural and graphical images, enable 2-D graphics to be implemented at high speed, and also provide 3-D graphical display capability.

The Q2i inherits from the Q2 such features as use of a double-buffer architecture(*7) to implement real-time drawing, direct connection of DRAM, functions for TV- synchronized display and sync signal generation, a built-in color palette, and color space conversion (YUV -> RGB). Use of a 144-pin QFP plastic package enables a high-performance display system to be configured at low cost. These features enable a wide range of multimedia terminal graphics processing systems-including car navigation systems, medium-definition OA products such as network computers, and AV equipment including industrial equipment display systems, Internet TVs, and karaoke systems-to be implemented in compact form and with a high level of drawing performance. The Q2i uses a 0.6 micron 2- aluminum-layer CMOS process. Future development plans include a 66 MHz version in addition to the present 33 MHz version.

<Notes>
1. Accelerator: A chip that assists microcomputer operation by providing mechanisms for shortening processing time.
2. Geometrical processing: Relating to numeric values in coordinate conversion, including vertex parallel shifting and rotation processing.
3. Rendering processing: This is processing that draws lines and surfaces in graphics memory to represent the target figure.
4. Q2 (Quick 2D Graphics Renderer): Initial product in the Q Series A 2-D graphics renderer chip that enables external graphics memory capacity to be reduced by more than 50%, and is also capable of 3-D graphical display.
5. Unified graphics memory architecture: A method of managing data of different formats in the same memory. Data of different formats includes natural images and other color graphics, font patterns, display strings (drawing command strings), and figures created by drawing.
6. Polygon: A graphic unit used in expressing drawing processing time. The size of one unit varies depending on the graphic. For example, in the case of a surface, a rectangular area of 20 x 25 pixels is taken as a single-unit polygon, and the polygon index indicates how many polygons of this size can be processed per unit time.
7. Double-buffer architecture: An architecture in which two areas-one used for drawing and one for display-are provided in graphics memory, and their roles are switched at regular intervals. This architecture enables display processing and rendering processing to be carried out in intersecting fashion.

<Application Product Examples>

• Small-screen OA products (network computers, etc.)
• Car navigation systems
• AV products (Internet TVs, karaoke systems)
• Industrial equipment display systems

<Pricing in Japan>

Catalog No	Sample Price (Yen)
HD64412F	3,000

<Features>
1. SuperH-compatible, enabling implementation of compact, high-speed graphic display systems
The Q2i is provided with high-performance rendering functions with the addition of texture mapping, enabling 3-D graphical display. A SuperH-compatible interface function, memory interface, and display control functions are also included on-chip.
2. Built-in background display function
The Q2i includes a background display function that enables the reuse of unchanged screen data, and high-speed smooth-scroll background display in 1/60 second units.
3. Improved SuperH family interface
The interface to the SuperH microcomputer has been revised for greater ease of use.
4. Greater ease of use of drawing commands
A temporary halt and restart function for drawing processing has been added, and drawing functions have been enhanced, greatly improving ease of use in a SuperH family chip set.
5. Software and pin upward-compatibility with Q2
The Q2i inherits the Q Series features of unified graphics memory architecture and double-buffer architecture, enabling Q2 software to be run without modification. The pin arrangement and package are also the same, making board redesign unnecessary.

<Specifications>

Item			Specification
Maximum clock frequency	Drawing system internal operation		33 MHz,16.5 MHz x 2 (PLL used), 8.25 MHz x 4 (PLL used)
	Display system internal operation (display dot clock)		16.5 MHz (16.5 MHz, 16.5 MHz x 1/2)
Drawing capability (with background display)			Polygon drawing capability (25 x 20 pixels): 15,000/sec (10,000/sec) Line drawing capability (10 dots): 300,000 /sec (200,000/sec)
Display functions	Screen size		Minimum 320 x 240 dots (up to 640 x 480 dots)
	CRT scanning system		Non-interlace, interlace, interlace sync & video
	External synchronization		Master, TV synchronization
	Built-in color palette		Simultaneous display of 256 colors from 260,000
	Screen synthesis		One plane (in 8-bit/pixel mode)
Drawing functions	Drawing commands		4-vertex surface drawing, line drawing, work surface drawing, work line drawing
	Color representation		Source: 1/8/16 bits per pixel, drawing: 8/16 bits per pixel, work: binary
	Register setting		Current pointer setting, local offset setting, clipping
	Sequence control		Jump, subroutine, drawing halt/restart
Interfaces	SuperH family	Command/data transfer	Performed by DMA transfer (single address) or SuperH family microcomputer
		YUV -> RGB conversion	Input: 16 bits, 4:2:2 (Y, U, V, 8 bits each), output: 16 bits (R:5, G:6, B:5 bits)
		Delta-YUV -> RGB conversion	Input: 8 bits (d-Y, d-U, d-V, 4 bits each), output: 16 bits (R:5, G:6, B:5 bits)
		Interrupt output	Synchronization detection, frame detection, DMA transfer end, command error, vertical blanking, command end, command abort
		CPU interface	Can support either 3.3 V or 5 V operation SuperH family microcomputer
	Unified graphics memory	16-bit bus width EDO DRAM	Minimum 4 Mbits (selection of 4 Mbits x 1, 4 Mbits x 2, 16 Mbits x 1, or 16 Mbits x 2)
Process			0.6 micrometer CMOS
Package			144-pin QFP
Power supply voltage/temperature range			5.0 V +/-5%/0 C degrees to 70C degrees (I specification: 5.0 V+/-10%/-40C degrees to 85C degrees)

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