Hitachi, Ltd. (TSE:6501) today announced the HD74SSTL16857T address driver IC and 
HD74CDC857T PLL clock driver IC, which support DDR clock input and use the SSTL_2 
interface*1 for use with DDR synchronous DRAM*2modules. Sample shipments will begin 
in May 1999 in Japan.
These two ICs can be used to configure the driver block for high-speed DRAM modules 
(DIMMs*3).  They support a 150 MHz clock rate at a low voltage of 2.5 V, enabling stable, 
high-speed DIMM data transfer to be achieved in workstations and servers.

With higher workstation and server system speeds and increasing CPU performance, 
DRAMs are also becoming faster, and there is a need for driver ICs capable of providing 
fast and stable transfer of large amounts of data to and from DIMMs.  Hitachi has previously 
released, as DIMM driver ICs, the HD74ALVC*4 Series of address driver ICs for address 
signal transmission, and the HD74CDC2509B/10B PLL clock drive ICs for clock signal 
supply, supporting systems with a 100 MHz clock rate.  

However, with the advent of DDR synchronous DRAM as the next generation of high-speed 
DRAM supporting even faster systems, there is a demand for DIMM driver ICs compatible 
with the SSTL_2 interface, an interface standard which supports DDR-compatible clock 
input and high-speed operation at 2.5 V.

In response to this demand, Hitachi is now releasing the HD74SSTL16857T address driver 
IC and HD74CDC857T PLL clock driver IC, supporting 150 MHz operation at a low 
voltage of 2.5 V, for use with DDR-type synchronous DRAM DIMMs.  


The HD74SSTL16857T address driver IC supports a clock rate of 200 MHz, and the 
HD74CDC857T PLL clock driver IC, a clock rate of 150 MHz.  The HD74CDC857T has a 
built-in PLL circuit that enables the phase difference between the system clock and the 
internal clock of the DIMM to be reduced.  Support for SSC (Spread Spectrum Clock) 
modulation makes it possible to construct a system with a low level of EMI (Electro 
Magnetic Interference) noise.

These two new devices support DDR clock input.  Use of the SSTL_2 interface provides 
SSTL_2 compatibility of clock and data input in the HD74SSTL16857T and of clock input 
in the HD74CDC857T.  The HD74CDC857T allows clock input to be distributed among 
ten outputs.
A 0.35 micro meter CMOS process is used, enabling operation on power supply voltages of both 2.5 
V and 3.3 V.

To minimize the mounting area on the DIMM board, a thin (1.2 mm) 48-pin TSSOP 
package with a 0.5 mm lead pitch is used, for smaller and slimmer end-products.
Future plans include the development of PLL clock drivers supporting a 200 MHz clock 
rate, and driver IC products that will keep pace with advances in system design.

Hitachi, Ltd., headquartered in Tokyo, Japan, is one of the world's leading global electronics 
companies, with fiscal 1997 (ended March 31, 1998) consolidated sales of 8,417 billion yen 
($63.8 billion*).  The company manufactures and markets a wide range of products, 
including computers, semiconductors, consumer products and power and industrial 
equipment. For more information on Hitachi, Ltd., please visit Hitachi's Web site at 
http://www.hitachi.co.jp.
* At an exchange rate of 132 yen to the dollar.

Notes:	1. SSTL_2: Stub Series Terminated Logic_2; a low-voltage (Vcc = 2.5 V) interface standard
	2. DDR synchronous DRAM: Double data rate synchronous DRAM; data input/output is  
 	    synchronized with both rises and falls of the clock, enabling data transfer at twice the rate of 
    conventional synchronous DRAM.
	3. DIMM: Dual in-line memory module
	4. ALVC: Advanced low voltage CMOS

<Typical Applications>
High-speed, high-performance synchronous DRAM modules and memory boards (with 
DDR and SSTL_2 compatibility)

<Prices in Japan>
Product Code		Sample Price (Yen) 
HD74SSTL16875T		500                      
HD74CDC857T		750                       


<Specifications>
Model Name		HD74SSTL16875T		HD74CDC857T              
Function		14-bit SSTL_2		        PLL clock driver
			registered buffer                                            
Clock rate		200 MHz Max.		        50 to 150 MHz                
Logic interface
                                           ___ 			        ____    
			SSTL_2: DATA, CLK, CLK          SSTL_2: CLK, CLK, FBIN, FBIN                  
                                    _____ 
			2.5 V CMOS: RESET	        2.5 V CMOS: G                 
Power supply voltage	Vcc=2.3 to 3.6V		        AVcc=2.3 to 3.6V              
Process					          0.35 micro meter CMOS               
Package					          48-pin TSSOP