Hitachi, Ltd. (TSE: 6501) today announced, as an industry first, the release of the 
HM5425401BTT series (x 4-bit configuration), HM5425801BTT series (x 8-bit 
configuration), and HM5425161BTT series (x 16-bit configuration) 256-Mbit Double Data 
Rate synchronous DRAMs (DDR SDRAMs), for use as main memory, image memory, and 
cache memory in high-end personal computers, workstations, servers, etc. 
Sample shipments will begin in October 1999 in Japan.

These new products employ a 0.18 µm CMOS process and the DDR system in which data 
input/output is synchronized with the rise and fall of an external clock, enabling a data 
transfer rate of 266 Mbps per pin (with a 133 MHz clock frequency) to be achieved, twice the 
rate of synchronous DRAM for PC-133.  A JEDEC (Joint Electron Device Engineering 
Council) standard 66-pin, 400 mil*1TSOP-II package is used.

With the dramatic increase in system speed and CPU performance in personal computers, 
workstations, and similar equipment, there is a demand for higher transfer rates for the 
DRAMs used as main memory, image memory, and cache memory, to enable large quantities 
of data to be processed at high speed.  Against this backdrop, Hitachi has developed 256-
Mbit DDR SDRAMs as high-speed and large capacity DRAMs for the next generation of 
machines.

The HM5425401BTT series, HM5425801BTT series, and HM5425161BTT series employ 
a 0.18 µm CMOS process, with a x 4-bit, x 8-bit, and x 16-bit configuration, respectively.  
These devices operate in synchronization with an external clock, but data input/output is 
synchronized with both the rising and falling edges of the clock, enabling data to be 
transferred at twice the clock frequency.  

The operating frequencies of these products are 100 MHz and 133 MHz enabling data rates of 
200 Mbps/pin and 266 Mbps/pin -twice the clock rate-to be achieved.  These new 
synchronous DRAMs use an SSTL-2*2 interface to provide high-speed operation, and a 2.5 V 
power supply voltage for high speed and low power consumption. 



Future plans include the development of the modules using these 256-Mbit DDR SDRAMs 
and higher speed and larger capacity DDR SDRAMs .

Notes:	1. mil: 100 mil = 2.54 mm
	2. SSTL: Stub Series Terminated Logic 

< Typical Applications >
Main memory in high-end workstations,servers,etc.
Buffer memory for image processing
Cache memory

< Prices in Japan > For your reference only

Product Code	Operating frequency	Configuration	Sample Price (Yen)
HM5425401BTT-10	100MHz (PC200)	16M x 4 x 4banks	24,000
HM5425401BTT-75A	133 MHz(PC266, CL=2)	16M x 4 x 4banks	28,000
HM5425401BTT-75B	133 MHz(PC266, CL=2.5)	16M x 4 x 4banks	26,000
HM5425801BTT-10	100MHz (PC200)	8M x 8 x 4banks	24,000
HM5425801BTT-75A	133 MHz(PC266, CL=2)	8M x 8 x 4banks	28,000
HM5425801BTT-75B	133 MHz(PC266, CL=2.5)	8M x 8 x 4banks	26,000
HM5425161BTT-10	100MHz (PC200)	4M x 16 x 4banks	24,000
HM5425161BTT-75A	133 MHz(PC266, CL=2)	4M x 16 x 4banks	28,000
HM5425161BTT-75B	133 MHz(PC266, CL=2.5)	4M x 16 x 4banks	26,000

< Specifications >

Item	HM5425401BTT	HM5425801BTT	HM5425161BTT
Product configuration	16M x 4 x 4banks	8M x 8 x 4banks	4M x 16 x 4banks
Power supply voltage	2.5 V+/- 0.2V
Operating frequency	100 MHz, 133 MHz
Data transfer rate	200 Mbps/pin, 266 Mbps/pin
Burst length	2, 4, 8
Burst sequence	Sequential, interleaved
CAS latency	2, 2.5
Refreshing	8k cycles / 64 ms
Package	400-mil 66pin plastic TSOP-I I
Process	0.18µm CMOS