Hitachi, Ltd. (TSE: 6501) today announced the SH7615 32-bit microcomputer, featuring 
SH-DSP core and on-chip Ethernet controller for Ethernet connected equipment, as an 
enhancement of the SuperH(TM) RISC engine family*1 of RISC microcomputers.  Sample 
shipments will begin in March 2000 in Japan.

Use of the SH7615 will simplify the development of printers, network cameras, and similar 
equipment connected to Ethernet with a 10/100 Mbps transfer speed, and make it possible 
to create small, high-performance, low-power-consumption systems.

Data exchange via networks has come into general use for personal computers, printers, 
and similar OA and FA equipment.  However, more and more of the information to be 
processed consists of large-volume multimedia data including images, video, and voice, 
bringing the need for networks capable of high-speed transfer. The Ethernet is used as a 
standard network that meets this need, and has also become established as an interface for 
connection between network equipment.  In designing such devices, there is a demand for 
LSIs with network connectivity that will simplify system design.

Hitachi's SuperH RISC engine family have been recognized for low power consumption 
together with the high code efficiency provided by the use of 16-bit fixed-length 
instructions, and are used in various kinds of embedded systems, including OA and FA 
equipment.  Meanwhile, with the advent of the true multimedia age, there is a growing 
need of network interface for such equipment to offer network connectivity, as well as high 
performance.

Hitachi has developed the SH7615 in response to this demand, featuring a 32-bit SH-DSP 
core and an on-chip Ethernet controller that simplifies the design of the equipment 
connected to Ethernet.

The SH7615 incorporates MAC layer*2 section as Ethernet controller based on 
IEEE802.3*3, and uses the MII*4 standard interface for connection between the MAC layer 
and the physical layer.  The MII allows direct connection to a physical layer LSI 
supporting 10/100 Mbps transfer, simplifying the design of high-speed Ethernet equipment.

Also included on-chip are separate 512-byte FIFO*5 memories for transmitting and 
receiving, and a transmit/receive DMAC (direct memory access controller) that 
implements ring buffering*6.  This carries out DMA transfer of transmit/receive data 
between external memory and the Ethernet controller, reducing the load on the CPU and 
enabling an efficient network system to be implemented.

The SH7615 has a function for detecting Magic Packets(TM)*7 on the Ethernet.  A Magic 
Packet is a packet prescribed for performing "wake on LAN" from another device via the 
network, and the function of this Magic Packet detection simplifies the design of remotely 
activated network equipment.

The SH7615 uses 0.35 um CMOS process, and achieves high performance of 78 MIPS/120 
MOPS at a 3.3 V operating voltage and 60 MHz operating frequency, with a low power 
consumption of 690 mW.  In addition, three standby modes (sleep mode, standby mode, 
and module standby mode) enable power consumption to be further reduced when the 
device is idle.  The package is a 208-pin LQFP, facilitating the design of a compact, high-
performance, low-power-consumption network equipment.

Hitachi plans to develop additional SuperH(TM) family models for network equipment in the 
future.


Notes: 1. SuperH is a trademark of Hitachi, Ltd.
       2. MAC layer: Media Access Control layer.  A lower-level sub-layer within the data 
       link layer.  Specifies the frame transmission/reception method, frame format, data 
       error detection, etc.
       3. IEEE802.3: IEEE802 is the name of an IEEE (Institute of Electrical and 
       Electronics Engineers) committee for the promotion of LAN standardization.     
       IEEE802.3 is a CSMA/CD (Carrier Sense Multiple Access with Collision 
       Detection) 10 Mbps/100 Mbps Ethernet LAN specification standard.  With 
       CSMA/CD, the presence of the carrier is sensed before transmission, and if a 
       collision is detected during transmission, retransmission is executed after a given 
       interval.
       4. MII: Media Independent Interface.  The interface between the MAC layer and 
       physical layer.  Various kinds of LAN can be supported by changing the physical 
       layer interface LSI.
       5. FIFO: A first-in first-out buffer circuit.
       6. Ring buffering: A buffering method in which a memory area comprising a 
       number of data buffers is configured in the form of a ring, and controlled 
       mutually by the CPU and DMAC.
       7. Magic Packet is a trademark of Advanced Micro Devices, Inc.

< Typical Applications >
Information/OA product field: Terminal devices with built-in network functions, printers, 
cameras, FA products


< Prices in Japan >   (For Reference Only)
Product Code		Price in 10,000 Unit (Yen)
HD6417615AF		2,900