Hitachi, Ltd. (TSE: 6501) today announced to enhance total solutions with 
the SOCplanner (pronounced "S-O-C planner") system LSI platform.  SOCplanner is 
an integrated design platform that includes design and development rationalization, 
EDA tool enhancement, and the provision of reusable cores and IPs, and includes 
the latest hardware technologies and middleware, offering shorter development 
times and earlier market entry for system LSIs and user systems.

In recent years, the high-growth fields of multimedia devices, mobile phones, and 
digital consumer products have seen a demand for a variety of products offering 
better operability as well as higher functionality and smaller size.  Users have 
thus focused on developing a wide range of products and achieving major reductions 
in the development cycle through the use of System on Chip(SoC) technology.  
However, a major problem has been how to handle the longer design periods a
ssociated with the increasing scale and complexity of LSIs.

Against this backdrop, Hitachi has developed the integrated SOCplanner platform 
capable of offering SoC solutions including fast and dependable LSI design right 
through to user system development.  SOCplanner comprises the four elements 
described below: (1) system development environment, (2) LSI design environment, 
(3) silicon technology, and (4) CPU cores, IPs, OSs, and middleware common to 
these.

(1) System Development Environment
This comprises a series of development environments for system development by 
the user.  Development environments that previously differed according to 
the microcomputer or ASIC, although using the same CPU core, have been unified, 
and high-performance software development tools, a co-verification environment 
(concerted verification of hardware and software), and a common emulator 
(on-chip debugger) for different cores are provided.

(2) LSI Design Environment
This is a system LSI design environment based on the "One Pass" design method, 
in which upstream design verification effectiveness is improved, and design is 
carried out taking the next process into consideration, according to guidelines, 
for such design processes as  RTL floorplan*1, equivalence verification*2,  
static timing verification*3, and timing-driven layout*4, eliminating the need 
for design redos.  This enables the total development time for system LSI design 
to be halved (Hitachi figure).

(3) Silicon Technology
General-purpose products such as SuperH(TM)*5 and H8S microcomputers, as well as 
dedicated LSIs incorporating memory, analog modules, and IPs, are implemented 
with a common process, and a process with a 0.14 ¦Ìm gate length and 0.52 ¦Ìm 
metal pitch is used that offers major improvements over previous Hitachi products 
in integration level, power consumption, and operating frequency.

(4) CPU Cores, IPs, OS, and Middleware
SoCplanner provides modules central to a system, such as a SuperH or H8S CPU 
core, analog modules, and memory, as well as standard IPs including USB, 
IEEE1394, Ethernet, JPEG, and MPEG.  These modules can be interconnected by 
a SuperH/H8S common standard bus, allowing flexible system configuration to suit 
a wide variety of applications.  And it's allowing the user to employ them on 
silicon as pre-verified IPs.  In addition, a world-standard realtime OS and 
a comprehensive lineup of middleware are available, to provide a total solution 
that includes both hardware and software.

Hitachi already uses this platform for SuperH microprocessor development, and 
intends to use it in the future for the development of all next-generation 
systemLSIs, and to release successive products developed in this way.  Hitachi 
will also undertake the development of cores and IPs optimized for specific 
application areas, and will respond to a wide variety of user needs while 
pursuing a policy of openness to the user.By providing total solutions through 
the use of this platform, Hitachi's goal is for system LSI business to account 
for 60% of semiconductor sales in fiscal 2003.

Notes:	1.RTL floorplan: Inter-block wiring delay is estimated and timing 
          predicted by deciding on the rough block layout in the RTL 
          (Register Transfer Level) design stage.  The chip area and delay 
          power consumption can also be estimated.
	2.Formal verification: A tool that performs verification by 
          mathematically analyzing the equivalence between identical designs 
          and making a direct comparison, regardless of the description level.  
          Used for comparisons before and after logic synthesis, before and 
          after test circuit addition, and before and after clock tree 
          generation in the layout stage.
	3.Static timing verification: Within the function verification and 
          timing verification undertaken by conventional logic simulation, 
          timing verification alone is performed without test vectors, 
          at high speed and comprehensively.
	4.Timing-driven layout: Design redos are eliminated by means of 
          layout promoting processing that provides for compliance with
          timing (delay time)restrictions estimated in an upstream process.
	5.SuperH(TM): SuperH is a trademark of Hitachi, Ltd.