Hitachi, Ltd. (TSE: 6501) today announced the industry's first 12-Mbit low-power 
SRAM, the HM62V16768MI Series, for use in  mobile phones and portable information 
terminals.  Sample shipments will begin in November 2000 in Japan.  This new series 
supports high-density mounting and offers high-speed access at a low voltage, with 
an access time of 70 ns at 2.2 V (min.) operation.

At the same time, Hitachi announced 8-Mbit low-power SRAMs-the HM62V16512MI 
Series, featuring a 55/70 ns access time at 2.2 V (min.) operation, with sample 
shipments starting in September of this year in Japan, and the HM62A16512MI Series, 
featuring a 70 ns access time at 1.65 V (min.) operation, with sample shipments 
starting in December in Japan.  These three series use a 6.5 mm x 9.8 mm 48-pin CSP 
(Chip Scale Package)-the world's smallest class of package for 8-Mbit SRAM- that 
enables portable products to be made smaller and lighter.

With the rapidly increasing sophistication of mobile phone functions, there is a 
growing need for the SRAMs used for work memory, phone number lists, and image data 
storage in these products to achieve lower-voltage operation, lower current dissipation, 
and higher speed to keep pace with lower system voltages, while at the same time 
offering larger capacities than the current 4-Mbits together with higher mounting 
densities.

To meet these needs, Hitachi has developed a range of 12-Mbit/8-Mbit low-power 
SRAMs for use in mobile phones and portable information terminals.

The 12-Mbit low-power SRAM employs chip stacking technology to stack a 4-Mbit and 
an 8-Mbit low-power-consumption SRAM chip in a 48-pin CSP package.  With a package 
size of  6.5 mm x 9.8 mm, this package can be mounted in the same area as an 8-Mbit 
SRAM, enabling portable information terminals, with their need for large memory 
capacity, to be kept small.  The pin arrangement retains 4-Mbit and 8-Mbit upward
-compatibility, and the 4-Mbit and 8-Mbit chips can be controlled independently, 
allowing the SRAM to be used in a variety of ways.

The configuration is 768 kwords x 16 bits, and low-voltage, high-speed access is 
achieved, with an access time of 70 ns at 2.2 V (min.) operation.  

Using a 512 kword x 16-bit configuration and a 0.18 µm CMOS process, and employing 
circuit design techniques, the 8-Mbit low-power SRAMs offer low-voltage, high-speed 
operation of 55/70 ns at 2.2 V to 3.3 V (HM62V16512MI Series) or 70 ns at 1.65 V to 
2.2 V (HM62A16512MI Series).  Low-current operation is also achieved, with an 
operating current of 25 mA (max.) at 70 ns and a data retention current 
of 0.6 µA (typ.)/6.0 µA (max.), enabling data to be retained for long periods 
on battery backup in portable information devices and similar products.

The package used is a 6.5 mm x 9.8 mm 48-pin CSP-the world's smallest package 
class for 8-Mbit SRAM-for smaller, lighter system products.

Future plans include the development of low-power SRAMs offering even larger
 capacities.

< Typical Applications >

 Mobile phones
 Portable information terminals