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|Development of 50-nm Gate-length CMOS Technology for Mobile Equipment|
|- Novel structure improves high-speed, low-power and high-frequency performance -|
Japan, December 5, 2001 - Hitachi, Ltd. (NYSE:HIT) has developed
50-nm gate length CMOS (Complementary Metal Oxide Semiconductor) device
technology for high-speed, low-power, and high frequency applications,
in the 0.1m technology node.
This technology achieves high-speed operation at low power; low noise
performance for analog and RF applications using a novel Super Steep
Channel structure, and high-speed using an Offset Source/Drain structure.
It is expected to be suitable CMOS technology for the expanding mobile
Advances in system LSIs performance have contributed largely to the rapid expansion of the market for mobile equipment, which are becoming increasingly functionally sophisticated in recent years. The performance of system LSIs for mobile equipment is characterized by operation speed and power consumption. For mobile communication equipment, analog and high frequency performance are also required. To reduce power consumption of CMOS devices in a system LSIs, one effective method is to reduce the operating voltage, however this also results in a reduction in operation speed. In addition, although high integration can be achieved at low cost with CMOS devices, a high noise level problem has prevented their widespread use in analog/RF applications until now. However, as further enhanced functionality of mobile equipment is predicted, the development of CMOS technology that provides low-power, high-speed, and low-noise performance in high-frequency regions, has become an urgent issue.
Hitachi undertook research in CMOS platform technology for the 0.1m generation, and developed CMOS technology providing excellent low-voltage, high-speed and low noise performances.
Features of the technology are as follows:
Using this technology, a prototype CMOS device with a gate length of 50nm was fabricated.
When compared with previous CMOS, an 8% increase in speed was achieved. It was also confirmed that a 6 dB*3) decrease in noise was possible. This result shows the improvement in basic CMOS performance using a 50nm gate-length CMOS. The next step will be to integrate the device into an LSI, and further develop CMOS platform technology for mobile equipment.
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|WRITTEN BY Corporate Communications Division