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|Hitachi Releases 9/18-Mbit Zero Bus
Latency (ZBL) SRAMs for Communications
Applications, Achieving Industry's Top-Level Operating Speed of 250 MHz
| High-speed operation and low power consumption for buffer memory and table memory use in communications equipment such as routers and switches |
Tokyo, April 11, 2002 Hitachi, Ltd. (TSE: 6501) today announced a line of Zero Bus Latency (ZBL) SRAMs as synchronous SRAMs for communications equipment such as routers and switches, and the upcoming release of a total of eight series comprising the 9-Mbit HM66WP18512/3 and HM66WP36256/7 Series, and the 18-Mbit HM66WP18100/1 and HM66WP36512/3 Series. Sample shipments will begin in April 2002 for the 9-Mbit models, and in July 2002 for the 18-Mbit models.
These new products feature an absence of dead cycles when random read and write operations are repeated, and they are compatible with Zero Bus TurnaroundTM (ZBT®) SRAMs*1 of a similar type currently on the market.
They also offer the industry's top-level operating speed of 250 MHz for this type of SRAM, together with a low operating current of 250 mA (max.) for the 9-Mbit models and 300 mA (max.) for the 18-Mbit models at 250 MHz operation, enabling low system power consumption to be achieved.
The popularity of networks such as the Internet has brought higher communication equipment transmission speeds, with backbone line speeds now exceeding 10 Gbps. With such high-speed communications, fast memory is needed by communication equipment that carries out data routing and illegal data checking. There is thus a demand for high-speed, large-capacity, large-bit-width memory for use as buffer memory and table memory in communication equipment such as routers and switches.
Hitachi has previously been engaged in mass production of asynchronous fast SRAMs and Late-Write Synchronous SRAMs for use as secondary cache memory in servers and workstations, and has now developed a ZBL SRAMs to be released as the 9-Mbit HM66WP18512/3 and HM66WP36256/7 Series and 18-Mbit HM66WP18100/1 and HM66WP36512/3 Series.
[About these products]
These products are synchronous SRAMs that latch address and control signals from a processor or controller into the SRAM in synchronization with the system clock. They are compatible with Zero Bus TurnaroundTM (ZBT®) SRAMs, a particular feature being that no dead cycles occur when random read and write operations are repeated.
(1) High-speed operation
PBS (Pipelined Burst SRAM) types provided with
registers for input/output (HM66WP18512, HM66WP36256, HM66WP18100,
and HM66WP36512) and FT (Flow Through) types provided with registers
for input only (HM66WP18513, HM66WP36257 , HM66WP18101, and HM66WP36513)
are supported, and a standard LVTTL*2
interface is used as the input/output interface.
(2) Low power consumption
Power supply voltages of both 2.5 V and 3.3 V are supported for all series.
The packages used are a plastic 119-pin BGA (14 mm 22 mm) package with excellent thermal radiation characteristics, suitable for high-density mounting, and a surface-mount 100-pin LQFP (16 mm 22 mm). Both 9-Mbit and 18-Mbit models have the same package dimensions, and also offer pin arrangement upward compatibility that facilitates capacity upgrades.
For BGA package models, an IEEE standard test access port and boundary scan architecture (IEEE std. 1149.1-1990) are supported, enabling a compatible connection check to be conducted at the board level when module mounting is carried out.
Readers can find additional product information
on Hitachi's Web site at http://www.hitachisemiconductor.com/jp/eng/zbl
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|Information contained in this news release is current as of the date of the press announcement, but may be subject to change without prior notice.|
|WRITTEN BY Corporate Communications Division