|Listed by release date|
10th February 2003
|Prototype SRAM for mobile equipment achieves
world's lowest standby current
|- Prevention of cosmic ray-induced soft error leading to significant increase in reliability -|
Hitachi, Ltd. (NYSE:HIT)
has developed circuit technology for SRAM(Static Random Access Memory), used in cellular phones and personal digital equipment, which has achieved the world's lowest standby leakage current (16.7 femto-ampere (FA)/cell; femto: one quadrillionth, 10-15) and reduced cosmic ray-induced soft-error*1) rate to one two-hundreth (1/200) of previous levels. The technology developed is circuit technology which not only significantly reduces power consumption during standby, but also solves the problem of cosmic ray-induced soft error which arises as a result of increasing device miniturization.
SRAM is currently used as memory in cellular phones and personal digital equipment, due to its low power consumption features. However, as design-scales decrease in the pursuit greater SRAM memory capacity, several problems arise. Firstly, as the thickness of the gate insulation layer, of which the device is composed, becomes extremely thin at several nanometers (nm; 10-9m) or less, the leak current (the tunnel current between the gate and the silicon substrate) increases dramatically, causing power consumption during standby, i.e. when the SRAM is not operating, to increase. Another problem, is the appearance of the hitherto insignificant at ground-level problem of cosmic ray-induced soft error phenomenon. In the past, there was a period when soft error caused by alpha rays*2) was a problem for DRAM (Dynamic Random Access Memory). However, as the mechanism of the soft error caused by cosmic rays and alpha rays differ, it was not possible to apply the same error correction technology. Such problems were expected to become even more prominent with design rules beyond the 130nm-process which is already being used, and thus development of new technology to overcome them was an urgent matter.
In response to the need for new technology to overcome problems arising from increased miniaturization of SRAM devices, Hitachi has developed two new circuit technologies. Details of the technology are as follows.
When a 16 megabit SRAM prototype was made using these circuit technologies with a 130nm CMOS process, gate leakage current was decreased by 90%, and cosmic ray-induced soft error rate was reduced to one two-hundreth of previous levels. The standby current attained per cell was 16.7 fA/cell, the lowest in the world.
This technology can be applied not only to independent SRAM memory but also cache memory (on-chip memory) integrated in system LSIs, and is expected to be indispensable circuit technology for the 130nm process generation and beyond.
This technology was announced at the International Solid-State Circuits Conference (ISSCC), which was held from 9th February 2003, in San Francisco, California, U.S.A.
Explanation of Terms
|Information contained in this news release is current as of the date of the press announcement, but may be subject to change without prior notice.|
|WRITTEN BY Corporate Communications Division