Biography: Dr. ITOH Kiyoo

Kiyoo ITOH received his B.Sc. and D.Eng. degrees in Electrical Engineering from Tohoku University, Japan, in 1963 and 1976, respectively. He was a Visiting MacKay Lecturer at U.C. Berkeley in 1994, a Visiting professor at the University of Waterloo in 1995, and a Consulting Professor at Stanford University in 2000-2001.

He served on the IEEE Solid-State Circuits Award Committee from 1998-2000. He was a Member of the IEEE Fellow Committee from1999-2002, and an elected AdCom Member of IEEE Solid-State Circuits Society from 2001 to 2003. He is a Distinguished Lecturer of the IEEE Solid-State Circuits Society.

Since 1972 he has led RAM technology and low-power/low-voltage CMOS circuits at Hitachi Ltd: He was the lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4Kb to 64Mb. In the course of the developments he invented in 1974 the concept of folded data (bit)-line cell, which uses a pair of balanced data lines to eliminate various noise components, and presented the cell layout for a 64-Kb DRAM at the 1980 ISSCC. This cell has been adopted widely for almost all DRAM chips since then. He went on to develop key DRAM devices and circuits such as the triple-well structure, on-chip voltage down-converters, and low-power high-speed memory circuits such as a PMOS word driver and multi-divided data line. As early as 1988, as a pioneer, he initiated circuit inventions and developments to reduce subthreshold current of MOSFETs even for the active mode, which is highlighted today in low-voltage CMOS LSI design. Typical examples of the reduction are multi-threshold (Vt) CMOS logic, various gate-source (self) back-biasing schemes, and power switch that we take for granted today.

He holds 438 patents in Japan and US. He authored four books and two book chapters on memory designs, and contributed 168 IEEE-related technical papers and presentations, many of them invited.

Dr. Itoh has won 21 honors in US, Europe, and Japan. They include the IEEE Paul Rappaport Award in1984, the Best Paper Award of ESSCIRC90, the 1993 IEEE Solid-State Circuits Award, the 2006 IEEE Jun-ichi Nishizawa Medal, and the ISSCC2009 Service Award for his plenary talk. He is an IEEE Fellow. In Japan, his awards include the National Invention Award (Prize of the Patent Attorney's Association of Japan) in 1989, the Commendation by the Minister of State for Science and Technology (Person of Scientific and Technological Merits) in 1997, and the National Medal of Honor with Purple Ribbon in 2000 from the Emperor of Japan.

(revised 1^st April 2009 by K. Itoh)

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