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Hitachi Research & Development

Hitachi

Dr. Kiyoo ITOH

Dr. ITOH Kiyoo
Fellow, Hitachi, Ltd.

1-280 Higashi-Koigakubo,
Kokubunji-shi, Tokyo 185-8601, JAPAN

Tel: +81-(0)42-323-1111 Fax: +81-(0)42-327-7699
E-mail: kiyoo.itoh (please add ".pt@hitachi.com" to complete the address)

Date & Place of Birth:    January 1941 (Miyagi, Japan)

Employment & Professional Activities:

1999.06 - present Fellow, Hitachi Ltd.
2000.06.01 - 2002.05.31 Consulting Professor, Stanford University, U.S.A.
1995.06.01 - 1995.08.10 Visiting Professor, University of Waterloo, Canada
1994.04.01 - 1994.10.20 Visiting MacKay Lecturer, University of California, Berkeley, U.S.A.
1993.04.07 - 1994.03.31 Lectures at Graduate School of Engineering, Yamagata University, Japan
1992.04.01 - 1995.03.31 Lectures at Graduate School of Engineering, Waseda University, Japan
1989.09.21 - 1990.03.31 Lectures at Graduate School of Engineering, Musashi Institute of Technology
1997.02.21 - 1999.06.28 Senior Chief Scientist - Corporate Technology, Hitachi, Ltd.
1991.12.21 - 1997.02.20 Senior Chief Scientist, Central Research Laboratory, Hitachi, Ltd.
1983.02.21 - 1991.02.20 Chief Scientist, Central Research Laboratory, Hitachi, Ltd.
1976.08.21 - 1983.02.20 Senior Researcher, Central Research Laboratory, Hitachi, Ltd.
1963.04.01 Joined Central Research Laboratory, Hitachi, Ltd.

Professional Affiliations:

IEEE
2009 Plenary Speaker, ISSCC; 2008 Invited Speaker, TENCON; 2008 Invited Speaker, ICSICT; 2008 Invited Speaker, ICICDT; 2008 Invited Speaker, FTFC; 2008 Invited Speaker, ULIS; 2007 Invited Speaker, ICECS; 2007 Invited Speaker, EDSSC; 2007 Invited Speaker, ESSCIRC; 2007 Invited Speaker, FTFC; 2007 Invited Speaker, GLSVLSI; 2006 Invited Speaker, International SOI Conference; 2006 Invited speaker, NEWCAS; 2006 Invited Speaker, SSCS DLP; 2006 Invited Speaker, ISCAS; 2006 Invited Speaker, MIEL; 2006 Invited Speaker, National Chiao Tung University, IEEE CAS Taipei Chapter; 2006 Invited Speaker, National Taiwan University, IEEE CAS Taipei Chapter; 2005 Invited Speaker, Analog VLSI Workshop; 2005 Invited Speaker, FTFC; 2005 Invited Speaker, ICICDT; 2005 Invited Speaker, SSCS DLP, Patras (Greece); 2005 Invited Speaker, IEEE Workshop on Issues in Low Power VLSI Design, New Delhi; 2005 Invited Speaker, IEEE Workshop on Low Power Design Techniques, Bangalore; 2004 Invited Speaker, CICC; 2004 Invited Speaker, PATMOS; 2004 Plenary Speaker, SOCC; 2004 Invited Speaker and Panelist, NEWCAS; 2004 Tutorial Speaker, MELECON; 2004 ISSCC Panelist; 2004 Panelist, Symp. LSI Circuits; 2003 Invited Speaker, EDSSC; 2003 Panelist, Symp. VLSI Circuits; 2003 Invited Speaker, FTFC; 2003- SSCS Distinguished Lecturer; 2002 Invited Speaker, PATMOS; 2002 SSCS Nomination Committee; 2002 Keynote Speaker, ISLPED; 2002 Invited Speaker, MIEL; 2001 Invited Speaker, FTFC; 2001-2003 SSCS AdCom Member; 2000 Invited Speaker, CAS; 2000-2002 IEEE Fellow Committee; 1998-2000/2003- SSCS Award Committee; 1997 Tutorial Speaker, ISLPED; 1996 Invited Speaker, Symp. VLSI Circuits; 1995 ISLED Program Committee; 1994 Invited Speaker, Symp. Low Power Electronics (SLPE); 1994-1995 SLPE Program Committee; 1993 Invited Speaker, Workshop on Low Power Electronics; 1991 Invited Speaker, Int. Conf. Solid-Sate Devices and Materials; 1989 Invited Speaker, Int. Symp. VLSI Tech., Systems and Applications; 1989 Chair, ISSCC DRAM Session; 1987-1989 ISSCC Far East Program Committee; 1987/2002 ESSCIRC Corresponding Member; 1985/1999 Invited Speaker, ESSCIRC; 1984/1990/2003 ISSCC Panelist; 1981 Invited Speaker, Symp. VLSI Technology.

Others
2008 Invited Speaker, Tsinghua Information Forum; 2008 Tutorial Speaker, ICICDT; 2007 Invited Speaker, Dr. Dennard Benjamin Franklin Medal Ceremony; 2002 Invited Speaker, 3rd Int. Workshop on Interconnect Hierarchy, IMEC; 2001 Invited Speaker, VLSI02, IFIP Int. Conf. VLSI; 1999 Tutorial Speaker, POSEIDON Workshop (ESPRIT); 1998 Invited Speaker, 30th Anniversary of the 1-T Cell Invention by Dr. Dennard, IBM; 1998 Invited Speaker, "Fifty Years and Counting" Session, 18th Int. Symp. Silicon Mat. Sci. and Tech., ECS; 1997 Tutorial Speaker, VLSI1997, IFIP Int. Conf. VLSI; 1995/1996 Invited Speaker, Int. Conf. Microelect.; 1989/1990/1993 Invited Speaker, IEICE.

Editorial Boards:

1998-present Editor-in-chief of Advanced Microelectronics series, Springer-Verlag
1990 Guest Editor, IEICE
1981-1984 Publication Committee, IEICE

Education:

1976.11.11 D.Eng. Tohoku University, Electrical Engineering
1963.03.31 B.Sc. Tohoku University, Electrical Engineering

Awards & Recognitions:

2009.02.09 IEEE ISSCC2009 Service Award for his plenary talk
2008.05.27 Fellow, Honorary Member of IEICE
2007.05.25 Distinguished Achievement and Contributions Award of IEICE
2006.06.24 IEEE Jun-ichi Nishizawa Medal for pioneering contributions to dynamic random access memory (DRAM) cell structures and architecture
2005.09.21 Fellow of IEICE
2003.11.05 The Significant Invention Award, Tokyo Section of Japan Institute of Invention and Innovation (JIII) for subthreshold-current reduction circuits
2001.10.26 The Significant Invention Award, President of Tokyo Section of JIII for DRAM voltage-down converter
2000.10 The Significant Invention Award, Governor of Yamanashi-prefecture, Yamanashi Section of JIIII for PMOS boosted word driver
2000.05.16 National Medal of Honour with Purple Ribbon for the folded data-line DRAMs (Japanese Government)
1997.04.16 Commendation by the Minister of State for Science and Technology to Persons of Scientific and Technological Merits for the folded data-line cell
1996.01.01 IEEE Fellow; for seminal and sustained contributions to high-density DRAMs
1995.10.20 The Significant Invention Award, President of Tokyo Section of JIII for voltage-down converter
1994.05.14 Best Paper Award of IEICE for voltage-down converter
1993.02.24 IEEE Solid-State Circuits Award for technical contributions to folded data-line circuits and the developments of high-density DRAMs
1991.09.10 Best Paper Award of the 1990 European Solid-Circuits Conference for 1.5-V 64-Mb DRAM
1990.11.13 The best of what's new, Popular Science (USA) for 1.5-V 64-Mb DRAM
1990.05.19 The Outstanding Achievement Award of IEICE for multi-megabit DRAMs
1989.06.06 The National Invention Award, Prize of the Patent Attorney's Association of Japan, for invention in DRAMs
1988.10.20 The Significant Invention Award, Tokyo Section of JIII for the folded data-line cells
1988.10.01 The Prize of the Governor of Tokyo for for development of new technology
1985.06.17 1984 IEEE Electron Devices Society Paul Rappaport Award for a corrugated capacitor cell (CCC)

Patents & Papers:
Dr. Itoh holds 230 patents in Japan, and 208 patents in the U.S. including seminal RAM circuits such as the folded data line, on-chip voltage-down converter, and gate-source self-back biasing schemes to reduce sub-threshold current. He has authored four books and two book chapters on memory designs, and more than 168 IEEE-related technical papers and presentation including over 60 invited talks.

Research Interests:
*Studies of low-power/low-voltage CMOS LSIs and high-density RAMs.

(revised 1st April 2009 by K. Itoh)