| (1) |
K. Itoh and H. Sunami, "High Density Memory Cell Structure," presented at the 1981 Symposium on VLSI Technology, Hawaii, September 1981. |
| (2) |
K. Itoh, "Power Supply Constraints in Megabit DRAMs of the Future," presented at ESSCIRC'85, Toulouse, September 1985. |
| (3) |
K. Itoh, "Trends in Megabit DRAM Circuit Design," presented at the International Symposium on VLSI Technology, Systems and Applications, Taiwan, May 1989. |
| (4) |
K. Itoh, "The State of the Art and Perspectives for Megabit DRAMs," IEICE, SDM 89-25 (June 1989): 39-44. |
| (5) |
Y. Nakagome and K. Itoh, "Low-voltage High-speed Circuit Technology for 64Mb DRAMs," presented at IEICE, ED 90-73, August 1990. |
| (6) |
K. Itoh, "Reviews and Prospects of Deep Sub-Micron DRAM Technology," the 1991 International Conference on Solid State Devices and Materials, Extended Abstracts, (August 1991): 468-471. |
| (7) |
K. Itoh, M. Aoki, T. Matsumoto and M. Yamamura, "Trends in Sub-halfmicron DRAM Chip Design Technology," IEICE Spring Convention Tech. Dig. (March 1993): 10-23. |
| (8) |
M. Aoki and K. Itoh, "Low-Voltage, Low-Power ULSI Circuit Techniques," IEICE Tech. Report, ICD 93-39 (June 1993): 43-50. |
| (9) |
K. Sasaki and K. Itoh, "Low-Power RAMs," presented at the Workshop on Low Power Electronics, Phoenix, August 1993. |
| (10) |
K. Itoh, "A series of lectures on memory chip design," University of California, Berkeley, May-September 1994. |
| (11) |
K. Itoh, K. Sasaki and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies, Symposium on Low Power Electronics," Dig. Tech. Papers (October 1994): 84-87. |
| (12) |
K. Itoh, "A series of lectures on memory chip design," University of Waterloo, June-July 1995. |
| (13) |
K. Itoh, "Trend in VLSI Memory Technology," presented at the Int. Conf. on Microelectronics, Kuala Lumpur, December 1995. |
| (14) |
K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and Challenges of Multi-Gigabit DRAM Circuits," Symp. VLSI Circuits Dig. Tech. Papers, (June 1996): 2-7. |
| (15) |
K. Itoh, "Limitations and Challenges of Multi-Gigabit Memory Technology," presented at the Int. Conf. Microelectronics, Cairo, December 1996. |
| (16) |
K. Itoh, "Low Voltage Memory Design," presented at ISLPED'97 Tutorial, August 1997. |
| (17) |
K. Itoh, "Ultralow-Voltage Memory Circuits," presented at VLSI'97 Tutorial, Gramado (Brazil), August 1997. |
| (18) |
K. Itoh et al., "Pathways to DRAM Design and Technology for the 21st Century," "Fifty Years and Counting" presented at the Session of Eighth Int. Symp. Silicon Materials Science and Technology, ECS, May 1998. |
| (19) |
K. Itoh, "The Future of DRAM Design and Technology," presented at the 30th Anniversary of the 1-T Cell Invention by Dr. Dennard, IBM Watson Research Center, May 1998. |
| (20) |
K. Itoh, "Low-Power Embedded Memories," presented at POSEIDON workshop (sponsored by ESPRIT), Italy, March 1999. |
| (21) |
K. Itoh et al., "VLSI Memory Technology: Current Status and Future Trends," ESSCIRC'99 Dig. Technical Papers, (September 1999): 3-10. |
| (22) |
K. Itoh et al., "Reviews and Prospects of High Density RAM Technology," presented at CAS2000, Sinaia (Rumania), October 2000. |
| (23) |
K. Itoh, "Special distinguished lecture series on memory chip design," Stanford University, April-May 2001. |
| (24) |
K. Itoh, "Trends in High Density RAM Technology," presented at FTFC2001, Paris, May 2001. |
| (25) |
K. Itoh and H. Mizuno, "Low-Voltage Embedded-RAM Technology: Present and Future" presented at VLSI2001, IFIP International Conference on Very Large Scale Integration, Montpellier (France), December 2001. |
| (26) |
K. Itoh, "Trends in Low-Voltage Embedded-RAM Technology," presented at MIEL2002, Nis (Yugoslavia), May 2002. |
| (27) |
K. Itoh, "Low-Voltage Memories for Power-Aware Systems," presented at ISLPED2002, Monterey, August 2002. |
| (28) |
K. Itoh, "Trends in Ultralow-voltage RAM Technology," presented at PATMOS2002, Sevilla (Spain), September 2002. |
| (29) |
K. Itoh, "Low-voltage Memories for Power-Aware Systems and Challenges to Interconnections," presented at the Third International Workshop on Interconnect Hierarchy, IMEC, October 2002. |
| (30) |
K. Itoh, "Trends in Low-Voltage RAM Circuits," presented at FTFC2003, Paris, May 2003. |
| (31) |
K. Itoh, "Trends in Low-Voltage RAM Circuits for Power-Aware Systems," presented at Low-Power Low-Voltage CMOS Workshop, Rousset (France), October 2003. |
| (32) |
K. Itoh, "Ultralow-voltage RAM Technology-Current Status and Future Trends," presented at EDSSC'03, Hong Kong, December 2003. |
| (33) |
K. Itoh, "Trends in low-Voltage RAM Circuits for Power-Aware Systems," presented at MELECON2004 (Tutorial Speaker), May 2004. |
| (34) |
K. Itoh, "Trends in Low-Voltage Embedded RAMs," presented at NEWCAS, June 2004. |
| (35) |
K. Itoh, "Reviews and Prospects of Low-Voltage RAM Circuits," presented at SOCC2004, September 2004. |
| (36) |
K. Itoh, "Low-Voltage Embedded RAMs - Current Status and Future Trends," presented at PATMOS2004, September 2004. |
| (37) |
K. Itoh, "Reviews and Future Prospects of Low-Voltage Embedded RAMs," presented at CICC2004, October 2004. |
| (38) |
K. Itoh, "Leakage Reduction Circuits for Low-Voltage Embedded RAMs," presented at IEEE Workshop on Low Power Design Techniques, Bangalore (India), February 2005. |
| (39) |
K. Itoh, "Leakage Reduction Circuits for Low-Voltage Embedded RAMs," presented at IEEE Workshop on Issues in Low Power VLSI Design, New Delhi (India), March 2005. |
| (40) |
K. Itoh, "Leakage Reduction Circuits for Low-Voltage Embedded RAMs," presented at IEEE SSCS Distinguished Lecturer Program, Patras (Greece), April 2005. |
| (41) |
K. Itoh, "Low-Voltage Embedded RAMs in the Nanometer Era," presented at ICICDT2005 Dig. Tech. Papers (May 2005): 235-242. |
| (42) |
K. Itoh, "Low-Voltage Embedded RAMs in the Nanometer Era," presented at FTFC2005, Paris, May 2005. |
| (43) |
K. Itoh, "Analog Circuit Techniques for RAMs - Present and Future," Analog VLSI Workshop, 2005 IEEJ, Dig. Tech. Papers, Bordeaux (October 2005): 1-6 |
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K. Itoh, "Low-Voltage Nano-Scale Embedded RAMs," presented at National Taiwan University, IEEE CAS Taipei Chapter, April 2006. |
| (45) |
K. Itoh, "Low-Voltage Nano-Scale Embedded RAMs," presented at National Chiao Tung University, IEEE CAS Taipei Chapter, April 2006. |
| (46) |
K. Itoh, "Reviews and Prospects of Low-Voltage Nano-Scale Embedded RAMs," MIEL2006, Proc. vol. 1 (May 2006): 77-81. |
| (47) |
K. Itoh, M. Horiguchi, T. Kawahara, "Ultra-Low Voltage Nano-Scale Embedded RAMs," presented at ISCAS2006, Kos (Greece), May 2006. |
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K. Itoh, "Ultra-Low Voltage Nano-Scale Embedded RAMs," presented at IEEE SSCS Distinguished Lecture Program, Fort Collins, June 2006. |
| (49) |
K. Itoh, "Ultra-Low Voltage Nano-Scale Embedded RAMs," presented at NEWCAS2006, Gatineau (Canada), June 2006. |
| (50) |
K. Itoh, "Impacts of FD-SOI on Deep Sub-100-nm CMOS LSIs - A View of Memory Designers," presented at 2006 IEEE International SOI Conference, Niagara, October 2006. |
| (51) |
K. Itoh, "Low-Voltage Limitations for Deep Sub-100-nm CMOS LSIs - A View of Memory Designers," presented at GLSVLSI2007, Stresa-Lago Maggiore (Italy), March 2007. |
| (52) |
K. Itoh, "The 1T1C DRAM - Past, Present, and Future," presented at Dr. Dennard Benjamin Franklin Medal Ceremony, Philadelphia, April 2007. |
| (53) |
K. Itoh, "Low-Voltage Limitations of Nano-Scale CMOS LSIs," presented at FTFC2007, Paris, May 2007. |
| (54) |
K. Itoh, "Low-Voltage Limitations of Memory-Rich Nano-Scale CMOS LSIs," presented at ESSCIRC2007, Munchen, September 2007. |
| (55) |
K. Itoh, "Low-Voltage Limitations of Nano-Scale CMOS LSIs: Current Status and Future Trends," presented at EDSSC2007, Tainan (Taiwan), December 2007. |
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K. Itoh, "Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs," presented at ICECS2007, Marrakech (Morocco), December 2007. |
| (57) |
K. Itoh, "Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs," presented at ULIS2008, Udine (Italy), March 2008. |
| (58) |
K. Itoh, "Impact of Variability on Voltage Scaling Limitations of Nano-Scale CMOS LSIs - A Personal View," presented at FTFC2008, Leuven (Belgium), May 2008. |
| (59) |
K. Itoh, "Driving the Front End of DRAM Development - In Quest of the Joy of Creation," presented at Tsinghua Information Forum, Hitachi Sponsored Lecture Series, Peking, May 2008. |
| (60) |
K. Itoh, "Low-Voltage Limitations and Challenges of Nano-Scale CMOS LSIs - A Personal View of Memory Designer," presented at ICICDT2008, Grenoble (France), June 2008. |
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K. Itoh, "Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs," presented at ICICDT2008 Tutorial, Grenoble (France), June 2008. |
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K. Itoh, "Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs," presented at ICSICT2008, Peking, October 2008. |
| (63) |
K. Itoh, "Voltage Scaling Limitations of Memory-Rich Nano-Scale CMOS LSIs," presented at TENCON2008, Hyderabad (India), November 2008. |
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K. Itoh, "Adaptive Circuits for the 0.5-V Nanoscale CMOS Era (Plenary talk at ISSCC2009)," ISSCC2009 Dig. Tech. Papers (February 2009): 14-20. |
| (1) |
K. Itoh and N. Saito, "Magnetization Creep in Composite Plated Wires," Trans. IECE '72/11, vol. 55-C, no. 11 (1972): 602-609. |
| (2) |
K. Shimohigashi, K. Itoh and K. Chiba, “Design of a 3-Transistor, 2.5 Line Per-Bit Dynamic MOS RAM,” Trans. IECE '75/6, vol. 58-C, no. 6 (1975): 327-334. |
| (3) |
K. Itoh and N. Saito, “Digit Line Cross Talk in a plated Wire Memory Stack using Ferrite Keeper,” Trans. IECE'76/6, vol. 59-C, no. 6 (1976): 384-390. |
| (4) |
K. Itoh, K. Shimohigashi, K. Chiba, K. Taniguchi and H. Kawamoto, "A High-Speed 16-Kbit N-MOS Random-Access Memory," IEEE J. Solid-State Circuits, vol. SC-11, no. 5 (October 1976): 585-590. |
| (5) |
H. Masuda, R. Hori, Y. Kamigaki, K. Itoh, H. Kawamoto and Katto, "A 5V-only 64K Dynamic RAM Based On High S/N Design," IEEE J. Solid-State Circuits, vol. SC-15 (1980): 846-854. |
| (6) |
H. Masuda, R. Hori, Y. Kamigaki and K. Itoh, "Single 5-V, 64K RAM with scaled-down MOS structure," IEEE Trans. Electron Devies, vol. ED-27, no. 8 (1980): 1607-1612. |
| (7) |
K. Shimohigashi, H. Masuda, Y. Kamigaki, K. Itoh, N. Hashimoto and E. Arai, "An n-well CMOS Dynamic RAM," IEEE Trans. Electron Devices, vol. ED-29, no. 4 (April 1982): 714-718. |
| (8) |
H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe and S. Asai, "A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories," IEEE J. Electron Device Letters, vol. EDL-4, no. 4 (April 1983): 90-91. |
| (9) |
K. Itoh and H. Sunami, "High-density one-device dynamic MOS memory cells," IEE Proc., vol. 130, Pt. 1, no. 3 (June 1983): 127-135. |
| (10) |
H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe and S. Asai, "A Corrugated Capacitor Cell (CCC)," IEEE Trans. Electron Devices, vol. ED-31, no. 6 (June 1984): 746-753. |
| (11) |
R. Hori, K. Itoh, J. Etoh, S. Asai, N. Hashimoto, K. Yagi and H. Sunami, "An experimental 1Mbit DRAM based on High S/N Design," IEEE J. Solid-State Circuits, vol. SC-19, no. 5 (October 1984): 634-640. |
| (12) |
K. Kimura, K. Itoh, R. Hori, J., Etoh and Y. Kawajiri, "Experimental 1Mbit DRAM using power reduction techniques," IEE Proc. vol. 132, Pt. 1, no. 1 (February 1985): 23-28. |
| (13) |
K. Kimura, R. Hori, J. Etoh, Y. Kawajiri and K. Itoh, "Reduction of Dynamic RAM Power Dissipation by a Multi-divided Data-Line Structure," Trans. IECE'85/12, vol. J68-C, no. 12 (1985): 1006-1915. |
| (14) |
K. Kimura, K. Itoh, R. Hori, J. Etoh, Y. Kawajiri, H. Kawamoto, K. Sato and T. Matsumoto, "Power Reduction Techniquies in Megabit DRAM's" IEEE J. Solid-State Circuits, vol. SC-21, no. 3 (June 1986): 381-389. |
| (15) |
K. Itoh and K. Kimura, "Power supply constraints in megabit DRAMs of the future," Revue Phys. Appl. France, 22 (1987): 15-19. |
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G. Kitsukawa, R. Hori, Y. Kawajiri, T. Watanabe, T. Kawahara, K. Itoh, Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda and H. Kawamoto, "An Experimental 1-Mbit BiCMOS DRAM," IEEE J. Solid-State Circuits, vol. SC-22, no. 5 (October 1987): 657-662. |
| (17) |
T. Kaga, Y. Kawamoto, T. Kure, Y. Nakagome, M. Aoki, H. Sunami and K. Itoh, "Half-Vcc sheath-plate capacitor DRAM cell with self-aligned buried plate wiring," IEEE Trans. Electron Devices, vol. 35 (August 1988): 1257-1263. |
| (18) |
M. Aoki, Y. Nakagome, M. Horiguchi, H. Tanaka, S. Ikenaga, J. Etoh, Y. Kawamoto, S. Kimura, E. Takeda, H. Sunami and K. Itoh, "A 60ns 16Mbit CMOS DRAM with a Transposed Data-Line Structure," IEEE J. Solid-State Circuits, vol. 23, no. 5 (October 1988): 1113-1119. |
| (19) |
S. Kimura, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, Y. Nakagome, M. Aoki, T. Kisu, H. Sunami and K. Itoh, "Optically-Delineated 4.2µm2 Self-Aligned Isolated-Plate Stacked Capacitor," IEEE Trans. Electron Devices, vol. 35 (October 1988): 1591-1595. |
| (20) |
M. Horiguchi, M. Aoki, H. Tanaka, J. Etoh, Y. Nakagome, S. Ikenaga, Y. Kawamoto and K. Itoh, "Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM," IEEE J. Solid-State Circuits, vol. 23 (October 1988): 1128-1132. |
| (21) |
Y. Nakagome, M. Aoki, S. Ikenaga, M. Horiguchi, S. Kimura, Y. Kawamoto and K. Itoh, "The Impact of Data-Line Interfence Noise on DRAM Scaling," IEEE J. Solid-State Circuits, vol. 23, no. 5 (October 1988): 1120-1127. |
| (22) |
Y. Kobayashi, K. Asayama, M. Oohayashi, R. Hori, G. Kitsukawa and K. Itoh, "Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM," IEEE Trans. Electron Devices, vol. 36, no. 4 (April 1989): 706-711. |
| (23) |
T. Watanabe, G. Kitsukawa, Y. Kawajiri, K. Itoh, R. Hori, Y. Ouchi, T. Kawahara and T. Matsumoto, "Comparison of CMOS and BiCMOS 1-Mbit DRAM Performance," IEEE J. Solid-State Circuits, vol. SC-24, no. 3 (June 1989): 771-778. |
| (24) |
G. Kitsukawa, K. Itoh, R. Hori, Y. Kawajiri, T. Watanabe, T. Kawahara, T. Matsumoto and Y. Kobayashi, "A 1-Mbit BiCMOS DRAM Using Temperature-Compensation Circuit Techniques," IEEE J. Solid-State Circuits, vol. SC-24, no. 3 (June 1989): 597-602. |
| (25) |
K. Takeuchi, K. Shimohigashi, E. Takeda, E. Yamasaki, T. Toyabe and K. Itoh, "Alpha-Particle-Induced Charge Collection Measurements for Megabit DRAM Cells," IEEE Trans. Electron Devices, vol. 36, no. 9 (September 1989): 1644-1650. |
| (26) |
T. Kawahara, G. Kitsukawa, H. Higuchi, Y. Kawajiri, T. Watanabe, K. Itoh, R. Hori, Y. Kobayashi and T. Matsumoto, "Substrate Current Reduction Techniques for BiCMOS DRAM," IEEE J. Solid-State Circuits, vol. 24, no. 5 (October 1989): 1381-1389. |
| (27) |
E. Takeda, K. Takeuchi, D. Hisamoto, T. Toyabe, K. Ohshima and K. Itoh, "A Cross Section of Alpha-Particle-Induced Soft-Error Phenomena in VLSI's," IEEE Trans. Electron Devices, vol. 36, no. 11 (November 1989): 2567-2575. |
| (28) |
M. Aoki, J. Etoh, K. Itoh, S. Kimura and Y. Kawamoto, "A 1.5-V DRAM for Battery-Based Applications," IEEE J. Solid-State Circuits, vol. 24, no. 5 (1989): 1206-1212. |
| (29) |
M. Aoki, S. Ikenaga, Y. Nakagome, M. Horiguchi, Y. Kawase, Y. Kawamoto and K. Itoh, "New DRAM Noise Generation Under Half-Vcc Precharge and its Reduction Using a Transposed Amplifier," IEEE J. Solid-State Circuits, vol. 24, no. 4 (1989): 889-894. |
| (30) |
S. Kimura, Y. Kawamoto, T. Kure, N. Hasegawa, T. Kisu, J. Etoh, M. Aoki, E. Takeda, H. Sunami and K. Itoh, "A Diagonal Active-Area Stacked Capacitor DRAM Cell with Storage Capacitor on Bit Line," IEEE Trans. Electron Devices, vol. 37, no. 3 (March 1990): 737-743. |
| (31) |
K. Takeuchi, K. Shimohigashi, H. Kurosawa, H. kozuka, T. Toyabe and K. Itoh, "Origin and Charactaristics of Alpha-Particle-Induced Permanent Junction Leakage," IEEE Trans. Electron Devices, vol. 37, no. 3 (March 1990): 730-736. |
| (32) |
K. Itoh, "Trends in Megabit DRAM Circuit Design," IEEE J. Solid-State Circuits, vol. 25, no. 3 (June 1990): 778-789. |
| (33) |
Y. Nakagome and K. Itoh, "Low-voltage High-speed Circuit Technology for 64Mb DRAMs," IEICE, ED90 73-80 (August 1990): 1-9. |
| (34) |
K. Takeuchi, M. Aoki, E. Kume, Y. Watanabe, T. Kaga and K. Itoh, "Alpha-Particle-Induced Charge Transfer Between n+ Regions in High-Density Trench DRAM with Isolated p-Well Structures," IEEE Trans. Electron Devices, vol. 37, no. 8 (August 1990): 1893-1901. |
| (35) |
G. Kitsukawa, K. Yanagisawa, Y. Kobayashi, Y. Kinoshita, T. Ohta, T. Udagawa, H. Miwa, H. Miyazawa, Y. Kawajiri, Y. Ouchi, H. Tsukada, T. Matsumoto and K. Itoh, "A 23-ns 1-Mb BiCMOS DRAM," IEEE J. Solid-State Circuits, vol. 25, no. 5 (October 1990): 1102-1111. |
| (36) |
M. Horiguchi, M. Aoki, J. Etoh, H. Tanaka, S. Ikenaga, K. Itoh, K. Kajigaya, H. Kotani, K. Ohshma, and T. Matsumoto, "A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier," IEEE J. Solid-State Circuits, vol. 25, no. 5 (October 1990): 1129-1135. |
| (37) |
M. Aoki, K. Takeuchi, Y. Nakagome, Y. Kawase, K. Itoh, S. Kimura, T. Kaga and Y. Kawamoto, "Evaluation of Alpha-Particle-Induced Charge Collection in 3-Dimensional DRAM Cells Excluding the Influence of Data-Line Interference Noise," Trans. IEICE, vol. J73-C-2, no. 5 (1990): 310-318. |
| (38) |
K. Takeuchi, M. Aoki, Y. Watanabe and K. Itoh, "Alpha-Particle-Induced Charge Collection in Scaled DRAM Cells with Advanced Structure," Solid-State Electronics, vol. 33, no. 11 (1990): 1477-1483. |
| (39) |
T. Masuhara, K. Itoh, K. Seki and K. Sasaki, "VLSI Memories: Present Status and Future Prospects," IEICE Trans. on Electronics, vol. E74, no. 1 (January 1991): 130-141. |
| (40) |
M. Horiguchi, J. Etoh, M. Aoki, K. Itoh and T. Matsumoto, "A Flexible Redundancy Technique for High-Density DRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 1 (January 1991): 12-17. |
| (41) |
T. Kaga, T. Kure, H. Shinriki, T. Kawamoto, F. Murai, T. Nishida, Y. Nakagome, D. Hisamoto, T. Kisu, E. Takeda, and K. Itoh, "Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAMs," IEEE Trans. Electron Devices, vol. 38, no. 2 (February 1991): 255-261. |
| (42) |
Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda and K. Itoh, "An Experimental 1.5-V 64-Mb DRAM," IEEE J. Solid-State Circuits, vol. 26, no. 4 (April 1991): 465-472. |
| (43) |
Y. Nakagome and K. Itoh, "Reviews and Prospects of DRAM Technology," IEICE Trans., vol. 74, no. 4 (April 1991): 799-811. |
| (44) |
Y. Nakagome, K. Itoh, K. Takeuchi, E. Kume, H. Tanaka, M. Isoda, T. Musha, T. Kaga, T. Kisu, T. Nishida, Y. Kawamoto and M. Aoki, "Circuit Techniques for 1.5-3.6-V Battery-Operated 64-Mb DRAM," IEEE J. Solid-State Circuits, vol. 26, no. 7 (July 1991): 1003-1010. |
| (45) |
T. Kawahara, Y. Kawajiri, G. Kitsukawa, Y. Nakagome, K. Sagara, Y. Kawamoto, T. Akiba, S. Kato, Y. Kawase and K. Itoh, "A Circuit Technology for Sub-10-ns ECL 4-Mb BiCMOS DRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 11 (November 1991): 1530-1537. |
| (46) |
K. Kimura, T. Sakata, K. Itoh, T. Kaga, T. Nishida and Y. Kawamoto, "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture," IEEE J. Solid-State Circuits, vol. 26, no. 11 (November 1991): 1511-1518. |
| (47) |
M. Horiguchi, M. Aoki, J. Etoh, K. Itoh, K. Kajigaya, A. Nozoe and T. Matsumoto, "Dual-Regulator Dula-Decoding-Trimmer DRAM Voltage Limiter for Burn-in Test," IEEE J. Solid-State Circuits, vol. 26, no. 11 (November 1991): 1544-1549. |
| (48) |
G. Kitsukawa, K. Yanagisawa, M. Nakamura, T. Akiba, Y. Kawajiri, K. Miyazawa and K. Itoh, "Design of ECL 1Mb BiCMOS DRAM," IEICE Trans., vol. J75-C-2, no. 1 (January 1992): 1-10. |
| (49) |
T. Kawahara, Y. Kawajiri, G. Kitsukawa, K. Sagara, Y. Kawamoto, T. Akiba, S. Kato, Y. Kawase and K. Itoh, "Deep-Submicrometer BiCMOS Circuit Technology for Sub-10-ns ECL 4-Mb DRAM's," IEEE J. Solid- State Circuits, vol. 27, no. 4 (April 1992): 589-596. |
| (50) |
H. Tanaka, M. Aoki, J. Etoh, M. Horiguchi, K. Itoh, K. Kajigaya, and T. Matsumoto, "Stabilization of Voltage Limiter Circuit for High-Density DRAM’s Using Miller Compensation," IEICE Trans. J75-C-2 (8) (August 1992): 425-433. |
| (51) |
H. Tanaka, M. Aoki, J. Etoh, M. Horiguchi, K. Itoh, K. Kajigaya, and T. Matsumoto, "Stabilization of Voltage Limiter Circuit for High-Density DRAM’s Using Pole-Zelo Compensation," IEICE Trans. E75-C, no. 11 (November 1992): 1333-1343. |
| (52) |
Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, "Sub-1-V swing internal bus architecture for future low-power LSI's," IEEE J. Solid-State Circuit, vol. 28, no. 4 (April 1993): 414-419. |
| (53) |
T. Watanabe, K. Kimura, M. Aoki, T. Sakata and K. Itoh, "A Single 1.5-V Digital Chip for a 106 Synapse Neural Network," IEEE Trans. Neural Networks, vol. 4, no. 3 (May 1993): 387-393. |
| (54) |
T. Watanabe, M. Aoki, K. Kimura, T. Sakata and K. Itoh, "The Advantage of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips," IEICE Trans. or Electronics, vol. E76-C, no. 7 (July 1993): 1206-1214. |
| (55) |
T. Kawahara, T. Sakata, K. Itoh, Y. Kawajiri, T. Akiba, G. Kitsukawa and M. Aoki, "A High-Speed, Small-Area, Threshold-Voltage-Mismatch Compensation Sense Amplifire for Giga-Scale DRAM Arrays," IEEE J. Solid-State Circuits, vol. 28, no. 7 (July 1993): 816-823. |
| (56) |
J. Tanaka, T. Toyabe, S. Ihara, S. Kimura, H. Noda and K. Itoh, "Simulation of Sub-0.1-μm MOSFET's with Completely Suppressed Short-Channel Effect," IEEE Electron Device Letters, vol. 14, no. 8 (August 1993): 396-399. |
| (57) |
M. Horiguchi, K. Sakata and K. Itoh, "Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's," IEEE J. Solid-State Circuits, vol. 28, no. 11 (November 1993): 1131-1135. |
| (58) |
K. Sakata, K. Itoh, M. Horiguchi and M. Aoki, "Subthreshold-current reduction circuits for multi-gigabit DRAM's," IEEE J. Solid-State Circuits, vol. 29, no. 7 (July 1994): 761-769. |
| (59) |
T. Sakata, K. Itoh, M. Horiguchi and M. Aoki, "Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's," IEEE J. Solid-State Circuits, vol. 29, no. 8 (August 1994): 887-894. |
| (60) |
K. Itoh, K. Sasaki and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies," Proc. IEEE, vol. 83, no. 4 (April 1995): 524-543. |
| (61) |
K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and Challenges of Multigigabit DRAM Chip Design," IEEE J. Solid-State Circuits, vol. 32, no. 5 (May 1997): 624-634. |
| (62) |
K. Itoh, "Reviews and Prospects of Low-Power Memory Circuits," (invited), Low-Power CMOS Design, A. Chandrakasan and R. Brodersen, Eds., Wiley-IEEE Press, Hoboken, NJ, (1998): 313-317. |
| (63) |
T. Sekiguchi, K. Itoh, T. Takahashi, M. Sugaya, H. Fujisawa, M. Nakamura, K. Kajigaya, and K. Kimura, "A low-impedance open-bitline array for multigigabit DRAM", IEEE J. Solid-Sate Circuits, vol. 37, no. 4 (April 2002): 487-498. |
| (64) |
Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh, "Reviews and Future Prospects of Low-Voltage RAM Circuits," IBM J. R&D, vol.47, no.5/6 (Sep. /Nov. 2003). |
| (65) |
R. Takemura, K.Itoh, T. Sekiguchi, S. Akiyama, S. Hanzawa, K. Kajigaya, and T. Kawahara, "Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation", IEICE Trans. Electron., vol. E90-C, no.4 (April 2007): 758-764. |
| (66) |
K. Itoh, "The History of DRAM Circuit Designs - At the Forefront of DRAM Development," IEEE Solid-State Circuits Society News, vol. 13, no. 1 (Winter 2008): 27-31. |
| (67) |
K. Itoh, "In Quest of the Joy of Creation," IEEE Solid-State Circuits Society News, vol. 13, no. 1 (Winter 2008): 32-36. |
| (68) |
K. Itoh, H. Kurata, K. Osada, and T. Sekiguchi, "Memory at VLSI Circuits Symposium," IEEE J. Solid-State Circuits, vol. 43, no. 4 (April 2008): 762-768 |
| (69) |
K. Itoh, "Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs," Solid-State Electronics, vol. 53, issue 4 (April 2009): 402-410. |
| (1) |
K. Itoh and N. Saito, "Disturb Properties of Composite Plated Wires," presented at AIP Conference on Magnetism and Magnetic Materials, Chicago, November 1971. |
| (2) |
K. Itoh, K. Shimohigashi, K. Chiba, K. Taniguchi and Y. Kawamoto, "A High-Speed 16K-bit NMOS RAM," ISSCC76, Dig. Tech. Papers (February 1976): 140-141. |
| (3) |
K. Itoh, R. Hori, K. Shimohigashi and Y. Tominaga, "A single 5V, 65ns, 16pin, 16-K-bit Dynamic N-MOS RAM," ESSCIRC'78, Dig. Tech. Papers (September 1978): 103. |
| (4) |
K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto and H. Katto, "A single 5V 64K dynamic RAM," ISSCC80, Dig. Tech. Papers (February 1980): 228-229. |
| (5) |
K. Shimohigashi, H. Masuda, Y. Kamigaki, K. Itoh, N. Hashimoto and E. Arai, "An n-well CMOS Dynamic RAM," IEDM, Dig. Tech. Papers (December 1980): 835-836. |
| (6) |
K. Itoh and H. Sunami, "High density memory cell structure," presented at the 1981 Symposium on VLSI Technology, Hawaii, September 1981. |
| (7) |
H. Sunami, T. Kure, N. Hashimoto, K. Itoh, Y. Toyabe and S. Asai, "A corrugated capacitor cell (CCC) for megabit MOS memories," IEDM, Dig. Tech. Papers (December 1982): 806-808. |
| (8) |
K. Itoh, R. Hori, J. Etoh, S. Asai, N. Hashimoto, K. Yagi and H. Sunami, "An Experimental 1Mb DRAM with On-Chip Voltage Limiter," ISSCC84, Dig. Tech. Papers (February 1984): 282. |
| (9) |
E. Takeda, K. Takeuchi, A. Hiraiwa, T. Toyabe, H. Sunami and K. Itoh, "Three Dimensional Leakage Current in Corrugated Capacitor Cells," Extended Abs. the 17th Conf. Solid State Devices and Materials, Tokyo (August 1985): 37-40. |
| (10) |
K. Itoh and K. Kimura, "Power supply constraints in megabit DRAMs of the future," ESSCIRC'85, Dig. Tech. Papers (September 1985): 130. |
| (11) |
H. Masuda, T. Toyabe, H. Shukuri, K. Ohshima and K. Itoh, "A full three-dimensional simulation on α-particle induced DRAM soft-errors," IEDM, Dig. Tech. Papers (December 1985): 496-499. |
| (12) |
E. Takeda, K. Takeuchi, E. Yamasaki, T. Toyabe, K. Ohshima and K. Itoh, "Effective Funneling Length in Alpha-Particle Induced Soft Errors," Extended Abs. the 18th Conf. Solid State Devices and Materials, Tokyo (August 1986): 311-314. |
| (13) |
Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda, R. Hori and K. Itoh, "Bipolar CMOS merged structure for high speed Mbit DRAM," IEDM, Dig. Tech. Papers (December 1986): 802-805. |
| (14) |
E. Takeda, K. Takeuchi, E. Yamasaki, T. Toyabe, K. Ohshima and K. Itoh, "The Scaling Law of Alpha-Particle Induced Soft Errors for VLSI's," IEDM, Dig. Tech. Papers (December 1986): 542-545. |
| (15) |
R. Hori, G. Kitsukawa, Y. Kawajiri, T. Watanabe, T. Kawahara, K. Itoh, Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda and H. Kawamoto, "An Experimental 35ns 1 Mb BiCMOS DRAM," ISSCC87, Dig. Tech. Papers (February 1987): 280-281. |
| (16) |
K. Takeuchi, K. Shimohigashi, E. Takeda, E. Yamasaki, T. Toyabe and K. Itoh, "Experimental Characterization of α-Induced Charge Collection Mechanism for megabit DRAM Cells," 1987 Symposium on VLSI Technology, Dig. Tech. Papers (May 1987): 99-100. |
| (17) |
E. Takeda, K. Takeuchi, T. Toyabe, K. Ohshima and K. Itoh, "Key Factors in Reducing Soft Errors in Megabit DRAMs-Funneling and Scalability," Proc. the 25th Annual Int. Reliability Phys. Symp. (June 1987): 207-211. |
| (18) |
T. Kaga, Y. Kawamoto, T. Kure, Y. Nakagome, M. Aoki, H. Sunami and K. Itoh "A 4.2μm2 Half-Vcc Sheath-Plate Capacitor DRAM Cell," IEDM, Dig. Tech. Papers, (December 1987): 332-335. |
| (19) |
M. Aoki, Y. Nakagome, M. Horiguchi, S. Ikenaga, J. Etoh, Y. Kawamoto, S. Kimura, E. Takeda, H. Sunami and K. Itoh, "An Experimental 16Mb DRAM with Transposed Data-Line Structure," ISSCC88, Dig. Tech. Papers (February 1988): 250. |
| (20) |
T. Toyabe, S. Ikenaga, M. Aoki, H. Masuda and K. Itoh, "Memory Cell Capacitance Simulation in Three Dimensions," 1988 Symposium on VLSI Technology, Dig. Tech. Papers (July 1988): 27-28. |
| (21) |
S. Ikenaga, M. Aoki, Y. Nakagome, M. Horiguchi, Y. Kawase, Y. Kawamoto and K. Itoh, "New DRAM Noise Generation under Half-Vcc precharge and its reduction using a Transposed Amplifier," presented at the 1988 Symposium on VLSI Circuits, August 1988. |
| (22) |
G. Kitsukawa, K. Itoh, H. Hori, K. Kawajiri, T. Watanabe, T. Kawahara, T. Matsumoto and Y. Kobayashi, "A 1-Mbit DRAM using temperature compensation circuit techniques," ESSCIRC'88, Dig. Tech. Papers (September 1988): 2-5. |
| (23) |
M. Aoki, J. Etoh, K. Itoh, S. Kimura and Y. Kawamoto, "A 1.5V DRAM for Battery-Based Applications," ISSCC89, Dig. Tech. Papers (February 1989): 238-239. |
| (24) |
K. Itoh, "Trends in Megabit DRAM Circuit Design," presented at the 1989 International Symposium on VLSI Technology, Systems and applications, Taiwan, May 1989. |
| (25) |
K. Itoh, "The State of the Art and Perspectives for Megabit DRAMs," IEICE, SDM 89-25 (June 1989): 39-44. |
| (26) |
K. Yanagisawa, G. Kitsukawa, Y. Kobayashi, Y. Kinoshita, T. Ohta, T. Udagawa, K. Ishii, H. Miwa, H. Miyazawa, Y. Ouchi, H. Tsukada, T. Matsumoto and K. Itoh, "A 23ns 1Mbit BiCMOS DRAM," ESSCIRC'89, Dig. Tech. Papers, SDM89 63-72 (September 1989): 7-12. |
| (27) |
Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda and K. Itoh, "A 1.5V Circuit Technology for 64Mb DRAMs," 1990 Symposium on VLSI Circuits, Dig. Tech. Papers (June 1990): 17-18. |
| (28) |
M. Horiguchi, M. Aoki, J. Etoh, H. Tanaka, S. Ikenaga, K. Itoh, K. Kajigaya, H. Kotani, K. Ohshima and T. Matsumoto, "A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier," 1990 Symposium on VLSI Circuits, Dig. Tech. Papers (June 1990). |
| (29) |
Y. Nakagome and K. Itoh, "Low-voltage High-speed Circuit Technology for 64Mb DRAMs," IEICE, ED90 73-80 (August 1990): 1-9. |
| (30) |
Y. Nakagome, K. Itoh, K. Takeuchi, E. Kume, H. Tanaka, T. Mushya, T. Kaga, T. Kisu, T. Nishida, Y. Kawamoto and M. Aoki, "Circuit Techniques for 1.5-3.6V Battery-Operated 64Mb DRAMs," ESSCIRC'90, Dig. Tech. Papers (September 1990): 157-160. |
| (31) |
K. Kimura, T. Sakata, K. Itoh, T. Nishida and Y. Kawamoto, "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture," ISSCC91 Dig. Tech. Papers (February 1991): 106-297. |
| (32) |
T. Kawahara, Y. Kawajiri, G. Kitsukawa, Y. Nakagome, K. Sagara, Y. Kawamoto, T. Akiba, S. Kato, Y. Kawase and K. Itoh, "A Circuit Technology for Sub-10ns ECL BiCMOS DRAMs," Dig. Symp. VLSI Circuits (May 1991): 131-132. |
| (33) |
M. Horiguchi, M. Aoki, J. Etoh, K. Itoh, K. Kajigaya, A. Nozoe and T. Matsumoto, "Dual-Regulator Dual-Decoding-Trimmer DRAM Voltage Limiter for Burn-in Test," Dig. Symp. VLSI Circuits (May 1991): 127-128. |
| (34) |
K. Itoh, "Reviews and Prospects of Deep Sub-Micron DRAM Technology," the 1991 Int. Conf. Solid State Devices and Materials, Extended Abstracts (August 1991): 468-471. |
| (35) |
T. Kawahara, Y. Kawajiri, G. Kitsukawa, K. Sagara, Y. Kawamoto, T. Akiba, S. Kato, Y. Kawase and K. Itoh, "Deep Sub-Micron BiCMOS Circuit Technology for Sub-10ns ECL 4-Mb DRAMs," ESSCIRC'91, Dig. Tech. Papers (September 1991): 29-32. |
| (36) |
Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi and M. Aoki, "Sub-1-V Swing Bus Architecture for future Low-Power ULSIs," Symp. VLSI Circuits Dig. Tech. Papers (June 1992): 82-83. |
| (37) |
K. Itoh, M. Aoki, T. Matsumoto and M. Yamamura, "Trends in Sub-halfmicron DRAM Chip Design Technology," IEICE Spring Convention Tech. Digest (March 1993): 10-23. |
| (38) |
K. Sakata, M. Horiguchi, and K. Itoh, "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's," Symp. VLSI Circuits Dig. Tech. Papers (May 1993): 45-46. |
| (39) |
M. Horiguchi, K. Sakata and K. Itoh, "Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI's," Symp. VLSI Circuits Dig. Tech. Papers (May 1993): 47-48. |
| (40) |
M. Aoki and K. Itoh, "Low-Voltage, Low-Power ULSI Circuit Techniques," IEICE Tech. Report, ICD93-39 (June 1993): 43-50. |
| (41) |
K. Sasaki and K. Itoh, "Low-Power RAMs," presented at the Workshop on Low Power Electronics, Phoenix, August 1993. |
| (42) |
T. Sakata, M. Horiguchi, M. Aoki and K. Itoh, "Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's," ESSCIRC Dig. Tech. Papers (September 1993): 33-36. |
| (43) |
K. Itoh, "A series of lectures on memory chip design," University of California, Berkeley, May-September 1994. |
| (44) |
K. Itoh, K. Sasaki and Y. Nakagome, "Trends in Low-Power RAM Circuits Technologies," Symposium on Low Power Electronics, Dig. Tech. Papers (October 1994): 84-87. |
| (45) |
K. Itoh, "A series of lectures on memory chip design," University of Waterloo, June-July 1995. |
| (46) |
K. Itoh, "Trend in VLSI Memory Technology," presented at the Int. Conf. on Microelectronics, Kuala Lumpur, December 1995. |
| (47) |
K. Itoh et al., "A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-VT, Boosted Storage Node and Dynamic Load," Symp. VLSI Circuits Dig. Tech. Papers (June 1996): 132-133. |
| (48) |
K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and Challenges of Multi-Gigabit DRAM Circuits," Symp. VLSI Circuits Dig. Tech. Papers (June 1996): 2-7. |
| (49) |
K. Itoh, "Limitations and Challenges of Multi-Gigabit Memory Technology," presented at the Int. Conf. Microelectronics, Cairo, December 1996. |
| (50) |
K. Itoh, "Low Voltage Memory Design," presented at ISLPED'97 Tutorial, August 1997. |
| (51) |
K. Itoh, "Ultralow-Voltage Memory Circuits," presented at VLSI'97 Tutorial, Gramado (Brazil), August 1997. |
| (52) |
K. Nakazato, P.J.A. Piotrowicz, D. Hasko, H. Ahmed, and K. Itoh, "PLED-Planar Localized Electron Devices," IEDM97 Dig. Tech. Papers (December 1997): 179-182. |
| (53) |
K. Itoh et al., "Pathways to DRAM Design and Technology for the 21st Century," "Fifty Years and Counting," presented at Session of Eighth Int. Symp. Silicon Materials Science and Technology, ECS, May 1998. |
| (54) |
H. Mizuta, K. Nakazato, P.J.A. Piotrowicz, K. Itoh, T. Teshima, K. Yamaguchi, and T. Shimada, "Normally-off PLED (Planar Localised Electron Devices) for non-volatile memory," Symp. VLSI Technology Dig. Tech. Papers (June 1998.): 128-129. |
| (55) |
K. Itoh et al., "VLSI Memory Technology: Current Status and Future Trends," ESSCIRC'99 Dig. Technical Papers (September 1999): 3-10. |
| (56) |
K. Nakazato, K. Itoh, H. Ahmed, H. Mizuta, T. Kisu, M. Kato, and T. Sakata, "Phase-State Low-Electron-Number-Drive Random-Access Memory (PLEDM)," ISSCC 2000 Dig. Tech. Papers (February 2000): 132-133. |
| (57) |
K. Itoh et al., "Reviews and Prospects of High Density RAM Technology," presented at CAS2000, Sinaia (Rumania), October 2000. |
| (58) |
T. Takahashi, T. Sekiguchi, R. Takemura, S. Narui, H. Fujisawa, S. Miyatake, M. Morino, K. Arai, S. Yamada, S. Shukuri, M. Nakamura, Y, Tadaki, K. Kajigaya, K. Kimura, and K. Itoh, "A Multi-Gigabit DRAM Technology with 6F2 Open-Bit-line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse," ISSCC2001 Dig. Tech. Papers (February 2001): 380-381. |
| (59) |
K. Itoh, "Special distinguished lecture series on memory chip design," Stanford University, April-May 2001. |
| (60) |
K. Itoh and H. Mizuno, "Low-Voltage Embedded-RAM Technology: Present and Future," Proc. of the 11th IFIP Int. Conf. on VLSI, Montpellier (France) (December 2001): 393-398. |
| (61) |
K. Itoh, "Trends in Low-Voltage Embedded-RAM Technology," MIEL2002 Dig. Tech. Papers, Nis (Yugoslavia) (May 2002). |
| (62) |
K. Itoh, "Low-Voltage Memories for Power-Aware Systems," ISLPED2002 Proc. Monterey (August 2002): 1-6. |
| (63) |
K. Itoh, "Trends in Ultralow-voltage RAM Technology," PATMOS2002 Dig. Tech. Papers, Seville (Spain), September 2002. |
| (64) |
K. Itoh, "Trends in Low-Voltage RAM Circuits," presented at FTFC2003, Paris, May 2003. |
| (65) |
K. Itoh, "Ultralow-Voltage Memory Technology," presented at EDSSC’03, Hong Kong, December 2003. |
| (66) |
K. Itoh, "Trends in Low-Voltage RAM Circuits for Power-Aware Systems," presented at MELECON2004 (Tutorial Speaker), May 2004. |
| (67) |
K. Itoh, "Trends in Low-Voltage Embedded RAMs," NEWCAS Dig. Tech. Papers (June 2004): 45-48. |
| (68) |
K. Itoh, "Reviews and Prospects of Low-Voltage RAM Circuits," presented at SOCC2004, September 2004. |
| (69) |
K. Itoh, "Low-Voltage Embedded RAMs-Current Status and Future Trends," PATMOS2004 Dig. Tech. Papers LNCS 3254 (September 2004): 3-15. |
| (70) |
K. Itoh, "Reviews and Future Prospects of Low-Voltage Embedded RAMs," CICC2004 Dig. Tech. Papers (October 2004). |
| (71) |
M. Yamaoka, K. Osada, K. Itoh, R. Tsuchiya, and T. Kawahara "Dynamic-VT, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application" SOI Conference Dig. Tech. Papers (October 2004): 109-111. |
| (72) |
K. Itoh, "Leakage Reduction Circuits for Low-Voltage Embedded RAMs," presented at IEEE Workshop on Low Power Design Techniques, Bangalore (India), February 2005. |
| (73) |
K. Itoh, "Leakage Reduction Circuits for Low-Voltage Embedded RAMs," presented at IEEE Workshop on Issues in Low Power VLSI Design, New Delhi (India), March 2005. |
| (74) |
K. Itoh, "Leakage Reduction Circuits for Low-Voltage Embedded RAMs," presented at IEEE SSCS Distinguished Lecturer Program, Patras (Greece), April 2005. |
| (75) |
K. Itoh, "Low-Voltage Embedded RAMs in the Nanometer Era," ICICDT2005 Dig. Tech. Papers (May 2005): 235-242. |
| (76) |
K. Itoh, "Low-Voltage Embedded RAMs in the Nanometer Era," presented at FTFC2005, Paris, May 2005. |
| (77) |
R. Takemura, K. Itoh, T. Sekiguchi, S. Akiyama, S. Hanzawa, K. Kajigaya, and T. Kawahara, "A 0.4-V High-speed, Long-retention-time DRAM Array with 12-F2 Twin Cell," VLSI Circuits Symp. Dig. Tech. Papers (June 2005): 362-365. |
| (78) |
K. Itoh, "Ultra-Low Voltage Nano-Scale Embedded RAMs," presented at IEEE SSCS Distinguished Lecture Program, Fort Collins, June 2006. |
| (79) |
K. Itoh, "Impacts of FD-SOI on Deep Sub-100-nm CMOS LSIs -A View of Memory Designers-," presented at 2006 IEEE International SOI Conference, Niagara, October 2006. |
| (80) |
R. Takemura, K. Itoh, and T. Sekiguchi, "A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifier," ISLPED Dig. Tech. Papers (October 2006): 123-126. |
| (81) |
K. Itoh, "Low-Voltage Limitations for Deep Sub-100-nm CMOS LSIs -A View of Memory Designers-," presented at GLSVLSI2007, Stresa-Lago Maggiore (Italy), March 2007. |
| (82) |
K. Itoh, "The 1T1C DRAM -Past, Present, and Future-," presented at Dr. Dennard Benjamin Franklin Medal Ceremony, Philadelphia, April 2007. |
| (83) |
K. Itoh, "Low-Voltage Limitations of Nano-Scale CMOS LSIs," presented at FTFC2007, Paris, May 2007. |
| (84) |
K. Itoh, "Low-Voltage Limitations of Memory-Rich Nano-Scale CMOS LSIs," presented at ESSCIRC2007, Munchen, September 2007. |
| (85) |
K. Itoh, "Low-Voltage Limitations of Nano-Scale CMOS LSIs: Current Status and Future Trends," presented at EDSSC2007, Tainan (Taiwan), December 2007. |
| (86) |
K. Itoh, "Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs," presented at ICECS2007, Marrakech (Morocco) December 2007. |
| (87) |
R. Tsuchiya, T. Ishigaki, Y. Morita, M. Yamaoka, T. Iwamatsu, T. Ipposhi, H. Oda, N. Sugii, S. Kimura, K. Itoh, and Y. Inoue, "Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Architecture," IEDM Dig. Tech. Papers (December 2007): 475-478. |
| (88) |
K. Itoh, "Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs," presented at ULIS2008, Udine (Italy) March 2008. |
| (89) |
K. Itoh, "Impact of Variability on Voltage Scaling Limitations of Nano-Scale CMOS LSIs -A Personal View-," presented at FTFC2008, Leuven (Belgium) May 2008. |
| (90) |
K. Itoh, "Driving the Front End of DRAM Development-In Quest of the Joy of Creation-," presented at Tsinghua Information Forum, Hitachi Sponsored Lecture Series, Peking, May 2008. |
| (91) |
K. Itoh, "Low-Voltage Limitations and Challenges of Nano-Scale CMOS LSIs -A Personal View of Memory Designer-," presented at ICICDT2008, Grenoble (France), June 2008. |
| (92) |
K. Itoh, "Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs," presented at ICICDT2008 Tutorial, Grenoble (France), June 2008. |
| (93) |
K. Itoh, "Impact of Variability on Voltage Scaling Limitations of Nano-Scale CMOS LSIs," presented at CMOS ET 2008, Vancouver (Canada), August 2008. |
| (94) |
K. Itoh, "Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs," presented at ICSICT2008, Peking, October 2008. |
| (95) |
K. Itoh, "Voltage Scaling Limitations of Memory-Rich Nano-Scale CMOS LSIs," presented at TENCON2008, Hyderabad (India), November 2008. |
| (96) |
K. Itoh, "Low-Voltage Scaling Limitations of Nano-Scale CMOS LSIs," presented at IEEE Distinguished Lecture, Perth (Australia), November 2008. |
| (97) |
K. Itoh, "Low-Voltage Scaling Limitations of Nano-Scale CMOS LSIs," presented at PEECS2008, Perth (Australia), November 2008. |
| (98) |
K. Itoh, "Adaptive Circuits for the 0.5-V Nanoscale CMOS Era (Plenary talk at ISSCC2009)," ISSCC2009 Dig. Tech. Papers (February 2009): 14-20. |
| (99) |
S. Akiyama, T. Sekiguchi, R. Takemura, A. Kotabe, and K. Itoh, "Low-Vt Small-Offset Gated Preamplifier for Sub-1-V Gigabit DRAM Arrays," ISSCC2009 Dig. Tech. Papers (February 2009): 142-143. |
