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Corporate InformationResearch & Development

May 13, 2013

Report from Presenter

COOL Chips ⅩⅥ (IEEE Symposium on Low-Power and High-Speed Chips) was held in YOKOHAMA, JAPAN on April 17-19, 2013. COOL Chips is held every year in Japan and is an international society specialized in low-power and high-speed chips. Presentations about FPGA (Field Programmable Gate Array) are increasing recently.

Fig. 1 Motivation

Yokohama Research Laboratory introduced a presentation entitled "Image Processing Hardware Design Framework and FPGA Implementation by Hierarchical Models".

The scanning electron microscope (SEM) is widely used for observing micro domain sharp of variety of samples. For the circuit of image processing of SEM, higher performance of image processing and a variety of processing functions are required. The highly precise estimation of the hardware performance is particularly important at development stage (Fig. 1).

For the purpose of searching for observation field of view, the observation time is shorted and operability is improved according to the coordinate of electron beam move fast (fast scan). However, for detecting element properties and detecting signal amplification, an acquisition image at the time of the fast scan may deteriorate. Using the image restoration processing to improve image deterioration for fast scan is suggested[1]. A hardware design framework of image processing is proposed to solve these problems as shown in shown in Fig. 2. The simulation could be performed from function verification to FPGA implementation. Each project of the proposed framework is designed based on an image processing hardware development environment which called DAIS (Digital Arithmetic development environment for Image and Signal processing), and it can perform a model design while verifying an image (Fig. 3).

Fig. 2 Hardware design framework

Fig. 3 Hardware development


The hardware design framework and the development environment are used for image processing of the image restoration filter. We performed logic synthesis using ISE® based on FPGA of the Virtex®4 series (XC4VSX55) made in Xilinx®. The HDL that used for implementation is generated by Simulink® HDL Coder according to the hardware reference model. The circuit scale of the image restoration filter is 9395 slices (38% of circuit placement rates). The circuit scale of the image restoration filter based on a target device model is 681 slices (2% of circuit placement rates). Compare with these two results, it is efficiency in reducing a circuit resource by a target device model.

From above introduction, we confirmed the efficiency of the proposed hardware framework for image processing by using model hierarchization.

(By HIRANO Katsunori)

Related Papers

  • [1] Oho,Eisaku;Kogakuin University,"Image restoration for TV-scan moving images acquired through a semiconductor backscattered electron detector",SCANNING : The Journal of Scanning Microscopies (2009)
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