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SuperH and SuperH-DSP Microprocessors for the Mobile Computing Age

Toru Baji, Semiconductor & Integrated Circuits Division, Hitachi, Ltd.
Norishige Kawashimo, Semiconductor & Integrated Circuits Division, Hitachi, Ltd.
Ikuya Kawasaki, Semiconductor & Integrated Circuits Division, Hitachi, Ltd.
Koki Noguchi, Semiconductor & Integrated Circuits Division, Hitachi, Ltd.

ABSTRACT

The Hitachi reduced instruction set computer (RISC) microprocessor (SuperH family; abbreviated to SH microcomputer) technology supporting mobile computing is described, with special attention on the SH-3 with a memory management unit (MMU) and the SuperH with digital signal processor (SH-DSP) where signal processing capability has been enhanced. Also described is the operating system (OS) and middleware which are essential for mobile computing. The MMU and translation lookaside buffer (TLB) in the SH-3 are described. These functions perform the logical/physical address translation and high-level memory management required on a high-performance OS. The recently announced Windows1) CE (Consumer Electronics) is one of the most promising OSs for the mobile age.

Also DSP performance enhancements in the SH-DSP, using the Harvard multiple bus architecture and flexible DSP parallel instructions are described. The SH-DSP can achieve a digital signal processing performance comparable to general purpose DSPs.

1) Registered trademark of Microsoft Corp.


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