—"SOCplanner": Reducing Time and Cost in Developing Systems—
| Tsuyoshi Shimizu | System Software Development & Engineering Dept., System LSI Business Div., Semiconductor & Integrated Circuits, |
| Yoshio Okamura | Design Technology Development Dept., System LSI Business Div., Semiconductor & Integrated Circuits, |
| Yoshimune Hagiwara | IP Technology Center, System LSI Business Div., Semiconductor & Integrated Circuits, |
| Akihisa Uchida | 2nd Device Development Dept., System LSI Business Div., Semiconductor & Integrated Circuits, |
The SOC (system-on-a-chip) design methodology allows the configuration of whole systems from one or several chips in order to realize SIP (system in package) modules or MCMs (multi-chip modules). To design such chips, Hitachi has developed the "SOCplanner" system-on-a-chip platform for the quick implementation of hardware and software at low cost. The platform consists of libraries, design tools and design methodologies for effective system design.
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The Hitachi Hyoron (Japanese Only) |
SOCplanner, System LSI, platform, 76C
