| Takafumi Tokunaga | Process Development Dept., Semiconductor Technology Development Operation, Device Development Center, |
| Katsutaka Kimura | ULSI Research Dept., Central Research Laboratory, |
| Jun Nakazato | Production Technology Research Laboratory, |
| Masaki Nagao, D. Eng. | Semiconductor Manufacturing Technology Operation Total Production Div., Semiconductor & Integrated Circuits, Hitachi, Ltd. |
In the 0.1 µm process generation, we are progressing toward what is being called the "system on a chip." The promotion of that trend requires more than the LSI technology for increasing the integration scale of CMOS (complementary metal-oxide semiconductor) devices as suggested in the ITRS (International Technology Roadmap for Semiconductors). Also required is progress in the development of new materials for finer patterning and core integration technology through intimate cooperation of technologies for design, device/process, and manufacturing and inspection equipment. That will make it possible to provide the customer with the best solution from among diverse goals and approaches. The 0.1 µm-generation LSI chips feature high integration scale, with CMOS gate lengths of 0.1 mm or less, the integration of DRAM (dynamic random access memory), flash memory, BiCMOS (bipolar CMOS), analog cores, etc., and eight or nine layers of multi-layer wiring. Another feature is the full use of new materials, of which high-κ (dielectric constant) gate insulation films, copper wiring and low-κ interlayer films are typical. Such issues in LSI fabrication and inspection technology can be classified into those related to processes for (1) larger integration scale, (2) use of new materials, (3) core mixing and those related to production technology for (4) shorter development turnaround time (TAT) and (5) lower cost.
Semiconductor, CMOS, 0.1µm, Process, Device
