| Shinichiro Kimura, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
| Digh Hisamoto, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
| Nobuyuki Sugii, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
Silicon semiconductor (MOSFET: metal-oxide semiconductor field-effect transistor) dimensions are approaching the nanometer scale. The gate electrode size has already been reduced to 50 nm or less for the most advanced 90-nm technology nodes, and for the 65-nm nodes the size is expected to be 25 nm. A new guideline to replace the scaling rule is needed, and making use of the strain effect or 3D device structure design have attracted attention as a means of meeting that need. Technology that makes use of material strain requires highly accurate evaluation technology for strain and control of defects possibly caused by the strain. Substrate etching is a very important process in achieving a 3D MOSFET. Nanometer-scale precision, removal of processed surface damage and evaluation technology for that are essential.
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Central Research Laboratory |
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The Hitachi Hyoron (Japanese Only) |
silicon, MOSFET, strain effect, SD device structure, scaling
