| Ryuta Tsuchiya, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
| Masaru Izawa | Advanced Technology Dept., Central Research Lab., |
| Shinichiro Kimura, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
Now with the availability of devices based on 65-nm node microfabrication technology, the miniaturization of silicon LSI further progresses into the nanometer range. There have been many proposals as to how the conventional constraints of legacy Si devices might be superceded. Considerable interest has focused on a device structure in which current channels are fabricated on a 3D substrate for implementing basic Si-LSI MOSFET devices, and now Hitachi has developed a new type SOI-MOSFET that not only exhibits the same effects as 3D structure channel MOSFET devices but also takes full advantage of substrate bias. Enormous interest has also focused on nonvolatile memory for an expanding range of applications to new products—particularly flash memory, the mainstay high-density memory used today—but the memory cells for storing charge in conventional floating gates is limited. This led us to a new approach in developing a memory based on charge-trapping film. While pursuing this kind of ground-breaking work transforming individual silicon devices, Hitachi is committed to developing and providing the best LSI manufacturing technology solutions.
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Central Research Laboratory |
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The Hitachi Hyoron (Japanese Only) |
SOI, non-volatile memory, 3D device, Fin FET, APC
