| Dai Hisamoto, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
| Nobuyuki Sugii, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
| Kazuyoshi Torii, Dr. Eng. | ULSI Research Dept., Central Research Lab., |
| Akio Shima | ULSI Research Dept., Central Research Lab., |
| Daisuke Ryuzaki | ULSI Research Dept., Central Research Lab., |
Now well into the early years of the 21st century, it has been four years since booster innovations were proposed as a way to extend and sustain CMOS performance gains that until now were achieved by reducing feature size, and development is under way on devices beyond the 2nd generation. Microfabrication development has been largely driven over this period by NAND type flash memory, and the pace of progress exceeded the projections of the ITRS (International Technology Roadmap for Semiconductors). Yet aside from strain engineering, none of the technologies anticipated as boosters are ready for practical implementation, and will not be introduced as anticipated by the ITRS time-line. In this paper we will consider the current status of research and development in 2007 on ULSI devices that defines the development of the latest fab equipment, and the direction this work will take in the years ahead.
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The Hitachi Hyoron (Japanese Only) |
CMOS roadmap, multigate MOSFET, strained-Si MOSFET, high-k/metal gate, interconnect technology
