| Hiromichi Enami | Etching Process Design Dept., Kasado Div., Nanotechnology Products Business Gr., |
| Masamichi Sakaguchi | Etching Process Design Dept., Kasado Div., Nanotechnology Products Business Gr., |
| Naoshi Itabashi | Advanced Technology Research Dept., Solution LSI Research Lab., Central Research Lab., |
| Masaru Izawa | Advanced Technology Research Dept., Solution LSI Research Lab., Central Research Lab., |
Maintaining the process accuracy of leading-edge semiconductor devices has recently become quite difficult. Dry etching, in particular, is facing many new challenges, such as the application of immersion lithography photo resists, dual metal materials, low-k and high-k materials, in addition to the basic requirements of cost and performance. Hitachi has developed excellent dry-etching equipment and application processes for manufacturing complicated devices that are based on a simplified chamber structure. These processes achieved the targets of 45-32-nm nodes while simultaneously accomplishing high throughput, high yield, and high productivity. A critical dimension uniformity of 1.8 nm, a line width roughness of 3.2 nm, and an isolation-dense bias of 1.0 nm have been achieved for gate etching. Etching rates of 300 nm/min, critical dimension shifts of <5.0 nm, and critical dimension uniformity of 3 nm have been attained for multilayer masks. Time-dependent changes could be reduced to 1.2% using process-control technology. Hitachi has already confirmed these features in 45-nm-node pre-manufacturing.
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Device Manufacturing & Process Control Equipment (Japanese Only) |
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Dry Etching System |
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APC (Advanced Process Control), Current Status and Issues |
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The Hitachi Hyoron (Japanese Only) |
semiconductor process, dry etch, hard mask, gate, advanced process control
