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Layout Design and Lithography Technology for Advanced Devices |
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AUTHORS |
| Shoji Hotta |
Nanoprocess Research Dept., Central Research Lab., Hitachi, Ltd. |
| Shinji Okazaki, Dr. Eng. |
Solution LSI Research Center, Central Research Lab., Hitachi, Ltd. |
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OVERVIEW |
The minimum feature size required for the most advanced semiconductor devices is now below half the exposure wavelength, and the optical lithography technology is facing its practical resolution limit. In this article, we review the current status of DFM and issues for further miniaturization. The role and requirements of metrology technology are also discussed. The layout design has been implemented following the device design rules required for device characteristics and layout design rules required for lithography technology. On the other hand, lithography technology has pursued accurate replication of designed patterns on a wafer. However, as required minimum feature sizes decrease to 45 nm or smaller, severe deformation of replicated patterns occur due to optical proximity effects, and the process window becomes very narrow for mass production. As a result, researchers in layout design technology needs to consider not only circuit characteristics but also lithography characteristics, which are part of DFM.
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TO READ THIS ARTICLE |
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CONTACT FOR INQUIRY |
Central Research Laboratory,
Hitachi, Ltd.
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RELEVANT SITE |
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KEYWORDS |
OPC, DFM, low k1 lithography, systematic defects, two-dimensional metrology
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