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October 2, 1997

Hitachi Releases HG74C Series 0.25-micrometers ASIC High Integration Density Cell-Based ICs

- Achievement of both low power and high integration density for ASICs with 10 million gates level, twice the scale of previous Hitachi products -

The basic ideal behind all Hitachi ASIC products is the provision of a rich cell library and a design environment that is both easy to use and achieves short development periods. Hitachi currently manufactures in volume products based on three ASIC series: the 0.8-micrometers CMOS process HG71 series, the 0.5-micrometers HG72 series, and the 0.35-micrometers HG73 series. Hitachi is also committed to promoting the system-on-chip concept. Hitachi released the HG73C series cell-based ICs, which add the 32-bit SH-3 (SH7708) RISC microprocessor and the 16-bit H8S microcomputer as CPU core modules in March this year, and then in July this year, Hitachi also released the HG73M series, which can include large- capacity DRAM modules and high-speed logic.

Hitachi releases the HG74C series of 0.25-micrometers ASICs, which achieves higher integration density and lower power to support the needs for miniaturization and improved performance in electronic equipment such as portable information equipment and multimedia equipment. At the same time as adopting a 0.25-micrometers CMOS process and using a 3 to 5 metal layer wiring technology, this series also adopts design tools and a logic synthesis optimization library developed jointly by Hitachi and VLSI Technology, Inc. This allows the HG74C series to implement on a single chip circuits that would be equivalent to 10 million gates if designed in random logic. The logic synthesis optimization library (the HDI (High Density Initiative) Library) is designed so that logic designed in a high-level language such as HDL can be converted efficiently to a highly integrated circuit. This is particularly effective when converting circuits designed with a commercially available logic synthesis tool to the gate level. This logic synthesis tool automatically selects a cell that is optimal for the required performance from a library of about 600 cells. As a result, ICs with efficient use of the chip area can be designed.
The HG74C series gate delay time is 90 picoseconds, which corresponds to a performance improvement of about 2.2 times over Hitachi's previous 0.35-micrometers, thus allowing this series to implement high-speed system ICs that operate at clock speeds of 200 to 300 MHz. HG74C series ASICs can be provided in a wide range of packages. In plastic packages, in addition to a standard QFP with from 100 to 384 pins, low thermal resistance QFP packages with built-in heat spreaders and BGA packages with up to 352 pins for high-density/high-speed applications are also available. In ceramic packages, the HG74C series ASICs can be provided in PGA packages with from 135 to 401 pins. These packages can also be used with heat sinks. For more compact and lower mounting heights, Hitachi is preparing CSPs (chip scale package) with from 112 to 264 pins.

In addition, to enable rapid high-precision design, Hitachi also provides both a RAM/ROM compiler for integrated design on engineering workstations and a high- precision simulation model. Future developments in this area will include support for CPU cores including the SuperH(TM) microprocessor, analog modules, DRAM, flash memory, and other circuits. Other features to be added will include support for high-speed RAM/DAC, ultrahigh-speed I/ O buffers (HSTL and PECL), and multi-pin BGA packages with on the order of 600 pins.

Note: 1. SuperH is a trademark of Hitachi, Ltd.

<Application Product Examples>
- Multimedia equipment: Games, high-performance image processing systems, DVD drives, set-top boxes, and musical instruments
- Portable information equipment: Portable communications devices, ATM LAN systems
- Industrial equipment: Robots, control systems

<Pricing in Japan>

Catalog No	Package	Number of gates	Unit price in lots of 10,000 (yen/unit)
HG74C	352-pin BGA	3,000 kG	40,000

<The HG74C series Library and Design Environment>
Up to 8M bits of SRAM as an embedded RAM can be embedded on a single chip. Also, a data path compiler is currently under development. This compiler will provide about a 20% increase in integration density and allow large-scale logic blocks to be generated easily. Additionally, Hitachi also provide a 300-MHz PLL (phase- locked loop) circuit to provide high-precision skew adjustment in large-scale high-speed ICs. In addition to standard CMOS/LV TTL (up to 24 mA) I/O buffers, slew rate control buffers, the PCI and SCSI buffers standard in PCs, and high-speed GTL buffers are also available. Based on Hitachi's basic ideal for ASIC design, the FFF (flexible, fast, and friendly) concept, Hitachi provides an even easier to use design environment with a proven track record so that large-scale logic circuits can be designed and verified easily. This design environment provides several features, including shorter design periods provided by high-precision timing simulation that takes both signal line resistance components and signal waveform distortion into account, timing design precision improved by an appropriate floor plan at the design stage, and the number of test design steps reduced significantly by the application of automatic diagnostic functions. Thus, high-quality designs can be achieved in short periods. This environment also supports boundary scans for user board tests.

Hitachi plans to support the following modules in the future.
- 32-bit SH series RISC microprocessor core, 16-bit H8S series microcomputer core
- Large-capacity DRAM and flash memory
- High-speed analog PLL, high-speed RAM/DAC, D/A and A/D converters
- USB, IEEE 1394, IrDA 1.1, PCI, PCMCIA, and other personal computer interfaces

<Specifications>

Item	HG74C
Process	0.25-micrometers CMOS process. Three to five metal layers
Power-supply voltage	2.5 V +/- 10%
Operating temperature	-20 to +75 C degrees
Operating frequency	200 to 300 MHz/2.5 V
Operating speed (internal cells)	90 picoseconds (standard load) at 2.5 V. RAM: 1.1 ns (1K byte, typical)
Maximum number of gates	Ten million
I/O interfaces	CMOS/ LV TTL/<PCI, GTL, SCSI></TD>
Compilers	RAM/<ROM, data path></TD>
Special functions	Shift-scan type automatic diagnosis, boundary scan, PLL, support for automatic generation of clocks with reduced skew.
Packages	QFP: 100, 136, 168, 208, 256, 296, 304, 344, and 384 pins BGA: 256, 352, <432>, <600> pins PGA: 135, 256, 299, 401 (heat sinks can be used), <600> and <1019> pins <CSP: 112, 144, 152, 168, 184, 192, 216, 232, 248, and 264 pins>

Note: Items enclosed in angle brackets (<>) are under development.

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