April 6, 1998
Hitachi Releases the HG75C Series 0.18-micrometer ASIC High Integration Density Cell-Based ICs
- Achievement of a high integration density for 25-million-gate ASICs, power consumption reduced to 1/5 of previous Hitachi cell based ICs, and high clock speed of 400MHz -
Based on this technology, Hitachi is planning to develop this series into a full-fledged system ASIC product that can include not only the SuperH(TM)*1 microprocessor CPU cores, but also DRAM, flash memory, and other complex circuits.
Hitachi is committed to promoting the system ASIC concept for multimedia equipment. Hitachi currently manufactures in volume 0.35- micrometer ASIC products such as the HG 73C series cell-based ICs, which add the SH-3 32-bit RISC processor and the 16-bit H8S microcomputer as CPU core modules, and the HG73M series, which can include large- capacity DRAM modules and high-speed logic.
Hitachi has developed and is releasing the HG75C series of 0.18- micrometer ASICs which support the need for miniaturization and improved performance in electronic equipment such as portable information equipment and multimedia equipment. At the same time as adopting an 0.18-micrometer CMOS process and using a 5 metal layer wiring technology, this series also adopts design tools and a logic synthesis optimization library. This allows the HG75C series to implement on a single chip circuit that would be equivalent to a level of 25 million gates if designed in random logic.
The logic synthesis optimization library (the HDI (High Density Initiative) Library) is designed so that logic designed in a high- level language such as HDL can be converted efficiently to a highly integrated circuit. This is particularly effective when converting circuits designed with commercially available logic synthesis tool to the gate level. This logic synthesis tools automatically selects a cell that is optimal for the required performance from a library of about 600 cells. As a result, ICs with efficient use of the chip area can be designed.
Although power dissipation is often a problem in high integration level ICs, by optimizing the power-supply voltage to 1.8 V, the HG75C series achieves a power dissipation of 0.04 microWatt per gate MHz. In addition to low power and low voltage, low stand-by current mode is also available in an option.
The HG75C series gate delay time is 75 picoseconds, which corresponds to a performance improvement of about 2-3 times over Hitachi's previous 0.35-micrometer cell-based IC series, thus allowing this series to implement high-speed system ICs that operate at clock speeds of 300-400 MHz. HG75C series ASICs can be provided in a wide range of packages. In plastic packages, in addition to a standard QFP with from 100 to 296 pins, low thermal resistance QFP packages with built-in heat spreaders.
For more compact and lower mounting heights, Hitachi is preparing CSP (chip scale package) with 112 to 264 pins. In addition, to enable rapid high-precision design, Hitachi also provides both a RAM/ROM compiler for integrated design on engineering workstations and a high- precision simulation model. Future developments in this area will include support for CPU cores including the SuperH microcomputer, analog modules, DRAM, flash memory, and other circuits. Other features to be added will include support for high-speed RAMDAC, ultrahigh-speed I/O buffers (HSTL and PECL), and multi-pin BGA packages with on the order of 600 pins.
Note1: SuperH is a trademark of Hitachi, Ltd.
Application Product Examples
Pricing in Japan
The HG75C Series Library and Design Environment Up to 8 Mbits of SRAM as an embedded RAM can be embedded on a single chip. Also, a data path compiler is currently under development. This compiler will provide about a 20% increase in integration density and allow large-scale logic blocks to be generated easily. Additionally, Hitachi also provides an over 250-MHz PLL (phase-locked loop) circuit to provide high-precision skew adjustment in large-scale high-speed ICs. In addition to standard CMOS/LVTTL (up to 24 mA) I/O buffers, slew rate control buffers, the PCI and SCSI buffers standard in personal computers, and high-speed GTL buffers are also available.
Hitachi provides an even easier to use the ASIC total design environment running on commercial EDA tools on EWS. In this environment, cycle based simulator and static timing analysis tools will be supported so that large-scale logic circuits can be designed and verified easily. This design environment provides several features, including shorter design periods provided by high-precision timing simulation that takes both signal line resistance components and signal waveform distortion into account, timing design precision improved by an appropriate floor plan at the first stage of design, and the number of test design steps reduced significantly by the application of automatic diagnostic functions. Thus high-quality designs can be achieved in short periods. This environment also supports boundary scans for user board tests.
Hitachi plans to support the following modules in the future.
Note: Items enclosed in angle brackets ( ) are under development.
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