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February 8, 2000
Development of high-speed system LSI technology for the sub-1V era
- New circuit technology to reduce LSI performance fluctuation -
Hitachi, Ltd. announced the development and verification in a fully functional 
microprocessor, of new circuit technologies that will increase the processing speed of system 
LSIs such as those used in personal digital assistants.  The technology controls the 
fluctuation in performance between individual LSIs which is expected to be an issue as 
operating voltages decrease to less than 1V, and thereby play a crucial role in achieving 
maximal system LSI performance in terms of high-speed and low power consumption.

This technology was applied to a microprocessor with 4,300,000 transistors capable of 
high-speed operation of more than 200MHz at 1.6V, and a 10% increase in speed was 
confirmed for operation at 1.5V.

As the heart of personal digital assistants and multimedia devices, it is vital to decrease 
the power consumption of system LSIs, and thereby extend battery time.  The most effective 
way to achieve this is to decrease the operating voltage, however, to maintain operating speed 
and decrease voltage, scaling down of the devices in the LSI becomes necessary.  In the 
dimension ranges of 0.18um, this raises new problems such as fabrication process deviations, 
supply voltage and operating temperature variations, which all degrade LSI performance.  
Being able to compensate for performance fluctuations is important for simultaneously 
realizing both high performance and low power consumption.

To tackle these issues, Hitachi has developed the following three circuit technologies:
1. "Speed Fluctuation Compensation" technology which allows a fixed operating speed to 
   be maintained despite fluctuations in supply voltage and temperature;
2. "Forward bias application to substrate" technology which increases LSI speed and 
   suppresses irregularities within the chip, and
3. "Standby Current Reduction" technology which suppresses the sub-threshold leakage 
   current of the LSI during standby mode.
Using the above technologies, it is possible to compensate for the performance fluctuation of 
low power consumption system LSIs in low supply voltage.  Also by significantly 
decreasing power consumption during standby mode, it is possible to simultaneously achieve 
higher speeds and lower power consumption.

The above was applied to a 4,300,000 transistor RISC-type microprocessor operating at 
1.6V, 200 MHz, 1,000 MIPS/W(*1), for verification.  Using technology (1), it was found that 
a change in operating frequency of 25% caused by a fluctuation in supply voltage from 1.5V 
to 1.8V could be compensated.  Further, using technology (2), a performance of 1,200 
MIPS/W was achieved despite a decrease in supply voltage to 1.5V by increasing the 
operating frequency by 25MHz.  Furthermore, using technology (3), the consumption 
current during standby mode was decreased to 30uA.

Although the effectiveness of these technologies were tested on a 1.6V system LSI, they 
will become indispensable in the 1V or less operation voltage generation, as supply voltages 
of future LSIs continue to decrease and fluctuation in LSI performance becomes an even 
greater problem.

These technologies for high-speed system LSIs will be presented at the International 
Solid State Circuits Conference (ISSCC 2000) to be held in San Francisco, U.S.A.

<Technical Details>
1. "Speed Fluctuation Compensation": Measure the operating speed within the LSI circuits 
   and control the substrate bias applied to the transistor substrate terminal in order to 
   achieve the desired speed.  By doing so, a stable operating speed can be achieved despite  
   fluctuations in transistor performance, variations in supply voltage and temperature, etc. 
2. "Forward bias application to substrate": A maximum forward bias(*2) of 0.5V is applied to 
   the substrate terminal of the transistor.  The effectiveness of the substrate bias control is 
   increased by this process, and performance fluctuations within the LSI, caused by the 
   short-channel effect,(*3) are reduced.  Further, high-speed performance can be achieved 
   during low voltage operation.  Further, by restricting the forward bias to 0.5V, negative 
   effects for CMOS circuits such as latch-up,กส*4กห are not observed.
3. "Standby Current Reduction": A 1.5V reverse bias is applied to the substrate terminal 
   during standby mode, when the LSI temporarily suspends operation.  Using this 
   technology, sub-threshold leakage current from the transistor is reduced and low power 
   consumption is achieved.

< Explanation of Terms>
(*1) MIPS: abbreviation for Million Instructions Per Second, an index of processor 
(*2) Forward bias: the direction of bias that results when the P-type semiconductor region is at 
     a positive voltage relative to the N-type region, the direction of a current flow with much 
     lower attenuation.
(*3) Short-channel Effect: a phenomenon where the threshold voltage of MOS transistors 
     suddenly decreases as the channel length becomes very narrow.
(*4) Latch-up: CMOS structures have an inherent vulnerability to a parasitic conduction 
     mechanism. Latch-up is a type of thyristor operating mechanism and is always possible to 
     trigger in n/p/n/p structures. If any one of the structures is triggered into latch-up, large 
     currents can flow and the results are usually irreversibly catastrophic for the whole chip.
(*5) Reverse bias: the direction of bias that results when the N-type semiconductor region is at 
     a positive voltage relative to the P-type region, the direction of a current flow with much 
     higher attenuation.

<Related Paper>
M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, K. Ishibashi,
"A 1,000-MIPS/W Microprocessor using Speed-Adaptive Threshold-Voltage CMOS with 
Forward Bias," 2000 IEEE International Solid-State Circuits Conference Digest of Technical 
Papers, pp. 420-421, 2000.

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