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Hitachi

Corporate InformationResearch & Development

November 24, 2020

Hitachi has successfully developed a prototype for the basic structure of a quantum bit*1 array using silicon semiconductors that will help enable large-scale integration of quantum bits for quantum computers. Until now, producing compact quantum computers has been difficult because large-scale integration entails increasing the amount of signal wiring for operating quantum bits. The prototype array attempted to achieve large-scale integration by arranging quantum bits in a two-dimensional state while limiting the increase in signal wiring by making shared use of signal wires that control multiple quantum bits through the application of CMOS semiconductor circuit technology.*2 Hitachi confirmed the stable formation of quantum dots*3 – which trap electrons during quantum computation – in the desired positions on the array. Going forward, Hitachi will work on testing quantum computation using this array structure and accelerate the development of silicon quantum computers with which large-scale integration is possible.

Background and issues addressed

  • With quantum computers, accumulating quantum bits on a large scale is important in order to solve complex computations. The achievement of large-scale integration is expected to make quantum computing applicable in a wide range of fields, including fast, efficient design and development of new materials and medications, financial risk calculations, and investment evaluations.
  • The R&D that Hitachi has conducted to date with the aim of enabling silicon quantum computers using CMOS semiconductor circuit technology has mainly taken place at the Hitachi Cambridge Laboratory.*4

Developed technologies

  • Compact two-dimensional quantum bit array structure that makes large-scale integration possible
  • Quantum bit structure that enables stable operation using semiconductor circuits

Verified effect

  • When the array structure was prototyped and operation was tested, it was found that quantum dots could be formed in the desired positions within the array by using shared gate electrodes.
  • It was found that by controlling quantum dot shape, it is possible to obtain the stable electrostatic coupling in double quantum dots*5 required for performing quantum computation while ensuring a sufficient voltage margin (0.2 V*6) for operating numerous quantum bits using semiconductor circuits.

Two-dimensional silicon quantum bit array structure

Two-Dimensional Silicon Quantum Bit Array Structure (Left-Hand Images) and Cross-Section Photos of Prototyped Quantum Bit Array (Right-Hand Images)


Published papers, conferences, events, etc.

These results have already been published as a featured article in the science journal Applied Physics Letters (23 April, 2020; Japan time; 24 April)

Acknowledgments

Some of the findings were obtained through research conducted in collaboration with the Tokyo Institute of Technology.

Details of developed technologies

1. Compact two-dimensional quantum bit array structure that makes large-scale quantum bits integration possible

Quantum dot is a fundamental structure for realizing a quantum bit. A key issue in achieving large-scale integration is the fact that as the number of quantum bits increases, the amount of signal wiring needed to operate the various quantum bits also increases, making it impossible to develop compact quantum computers. This array uses devices that form multiple quantum bits with signal wiring corresponding to word lines and bit lines*7, which intersect each other in the same manner as semiconductor memory such as SRAM and DRAM*8, and a structure that controls the coupling between quantum bits. Sharing signal wiring in this manner makes large-scale integration of quantum bits possible while limiting the increase in the wiring amount.

2. Quantum bit structure that enables stable operation using semiconductor circuits An issue in achieving stable operation of numerous quantum bits using semiconductor circuits was ensuring the voltage margin when forming and controlling the quantum dots required for quantum computation.

This structure makes stable operation of quantum dots possible based on optimization of the structure (gate length of the two types of gate electrode mentioned above, positional relationship, etc.) and the voltage applied to each gate electrode.


*1
Quantum bit: The smallest unit of quantum information. With conventional digital circuits (classical bits), information is retained in two states ("0" or "1"). However, with quantum bits, information may be represented by combining the states of "0" and "1" in the desired proportions.
*2
CMOS semiconductor circuit technology: a digital circuit system used in large-scale integrated circuits such as LSI and memory circuits.
*3
Quantum dots: An electron state in which the electrons are spatially trapped in all three-dimensional directions and the direction of movement is restricted.
*4
Research team led by the Hitachi Cambridge Laboratory demonstrates an innovative hybrid circuit for quantum computers (June 18, 2019), https://www.hitachi.com/New/cnews/month/2019/06/190618a.html
*5
Electrostatic coupling in double quantum dots: The state of two quantum dots being interlocked with each other. This is required for logic gate operations using two quantum bits when performing quantum computation.
*6
10 times the conventional voltage margin, based on Hitachi’s research (as of March 2020).
*7
Word lines/bit lines: Control signal lines for selecting a row from a memory cell array arranged two-dimensionally. Memory cells are placed at the intersections of word lines and bit lines, and reading/writing is possible by controlling word and bit lines corresponding to an address where reading/writing is performed. They are used with SRAM/DRAM, etc.
*8
SRAM/DRAM: A type of semiconductor memory. SRAM does not require stable refreshing (recovery operation), whereas DRAM retains information based on stable refreshing being performed.

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